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M.Matveev Rice University March 20, 2002

EMU Muon Port Card Project. M.Matveev Rice University March 20, 2002. MPC Functions. • One board per CSC Sector (8 or 9 chambers), • Resides in the middle of the peripheral VME 9U crate. • Receives up to 2 muons from each of 8 or 9 Trigger

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M.Matveev Rice University March 20, 2002

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  1. EMU Muon Port Card Project M.Matveev Rice University March 20, 2002

  2. MPC Functions • One board per CSC Sector (8 or 9 chambers), • Resides in the middle of the peripheral VME 9U crate. • Receives up to 2 muons from each of 8 or 9 Trigger Motherboards every 25 ns • Selects 3 best muons out of 18 possible • Transmits these 3 muons in ranked order to Sector Processors residing in the counting room over three 100 m optical cables every 25 ns

  3. MPC Block Diagram 9U x 400 MM BOARD VME J1 CONNECTOR VME INTERFACE UCLA MEZZANINE CARD (XCV600E) CCB CCB INTERFACE SORTING LOGIC INPUT ANDOUTPUT FIFO CCB TMB_1 OPTO SER TMB_2 CUSTOM PERIPHERAL BACKPLANE 3 OPTICAL CABLES TO SECTOR PROCESSOR TMB_3 OPTO SER TMB_4 TMB_5 TMB_6 OPTO SER TMB_7 FINISAR FTRJ-8519-1-2.5 OPTICAL TRANSCEIVERS TMB_8 TLK2501 SERIALIZERS FPGA TMB_9 SN74GTLP18612 GTLP TRANSCEIVERS

  4. Sorter FPGA MUON 1 DFF TMB 1 MUX PIPELINE MUON 1 DFF MUX 4 FIFO_B MUON 1 VME FIFO A VME MUX PIPELINE MUON 2 DFF MUON 2 DFF 4 VME FIFO A FIFO_B MUON 2 TMB 2 VME • • MUON 3 DFF • TMB 9 VME FIFO_B MUON 3 54 SORTER “3 OUT OF 18” CCB 9 VME CCB INTERFACE WINNER

  5. FPGA Requirements • 9 input links from Trigger Motherboards, 32-bit @ 80 MHz per link (288 inputs total) • 3 output links to data serializers, 16-bit @ 80 MHz per link (48 outputs total) • 1 output status link (winners) 9-bit @ 80 MHz to TMBs • Input and output FIFO buffers for testing purposes • Interfaces to VME and Clock and Control Board (CCB) (~75 inputs and outputs total for both) • FPGA should have ~470 input/output pins and ~28 Gbps total bandwidth

  6. TMB - to - MPC Frame Format

  7. MPC – to – SP Frame Format

  8. CSC Numbering scheme • In the present design the CSC_ID=1 corresponds to TMB1 on the peripheral backplane, CSC_ID=2 corresponds to TMB2 and so on T M B D M B T M B D M B T M B D M B T M B D M B T M B D M B M P C C C B T M B D M B T M B D M B T M B D M B T M B D M B 1 2 3 4 5 6 7 8 9

  9. Preliminary results of FPGA Design • Targeted to Xilinx XCV600E-7FG680 FPGA (UCLA mezzanine card) • 461/512 input/output pins used (89%) • 5009/6912 slices used (72%) • 42/72 BlockRAMs used (58%) • 44.13 Mhz maximum performance (FPGA Express synthesis) Latency • 100.0 ns (4.0 BX) total FPGA latency including: - 1.0 BX input latching @ 80MHz and multiplexing with FIFO - 1.5 BX sorting “3 out of 18” - 0.5 BX data merging - 0.5 BX output multiplexing and latching @80MHz - 0.5 BX data latching into TLK2501 serializers • 24 ns serialization delay (TLK2501 transmitter @ 80 MHz)

  10. MPC Board Design Status • GTLP Backplane Interface to 9 TMB’s (completely defined) • Mezzanine Card pin assignment done • A24D16 VME Interface based on glue logic (address latches, data buffers, comparators, DS/DTACK logic, CSR0) • CCB Interface is completely defined • Optical Data Format to SP has been agreed • Preliminary FPGA design is done (XCV600E-7FG680) • MPC draft specification is prepared • Schematic design ~80% completed • 6 free FPGA were obtained (Xilinx donation) • Mezzanine cards are ordered through UCLA

  11. CCB for Track Finder Crate • Same CCB for peripheral and Track Finder crates • 20 sets (main 9U board + Altera-based mezzanine card) have been fabricated so far • 15 boards are assembled and tested • 2 boards will be used for Track Finder tests (UF & Rice)

  12. Mezzanine Card ECP680-1102-630C ECP 680-1102-610B TTCrx ASIC operating voltage +5.0V +3.3V +5.0V Clock40Des1 jitter, ps (no BC, no L1A) 153 170 330 Clock40Des1 jitter, ps (BC commands + L1A) 183 215 360 TTCrx Clock40Des1 Jitter New TTCrx Old TTCrx

  13. Optical Test with TTCrx B I T 3 T T C V I T T C V X C C B ERROR • TTCrx • • O P T O O P T O • • PC • • • • 100 m Clock multiplier • • 40 Mhz • • VME 9U VME 6U 1 m COPPER CABLE OPTICAL CABLE 100 m • OLD AND NEW TTCrx BOARDS WERE TESTED WITH 40.00 Mhz CLOCK SOURCE FROM TTCvx MODULE • 40.00 Mhz CLOCK WAS MULTIPLIED BY 2 BY AV9170 CHIP • NO ERRORS OBSERVED IN PRBS TEST FROM ONE OPTOBOARD TO ANOTHER AT 80.00 Mhz (BER < 10-13 c-1)

  14. TTCrx Clock40Des1 Jitter Conclusion • Jitter is lower for the newest TTCrx ASIC (Version 3.1, 12/2001) • Jitter increases if the broadcast commands and L1A are transmitted from TTCvi/TTCvx • Jitter distribution for ASIC Ver.3.1 is close to gaussian. Jitter distribution for old ASIC looks differently • Jitter is lower if the new ASIC is powered from +5V • Jitter introduced by any of two TTCrx ASICs and other components in the clock distribution circuitry at our testing setup is tolerable for TLK2501 transceivers operating at 80.00 Mhz

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