Studio session 1 introduction to vhdl and related tools
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Studio Session 1: Introduction to VHDL and related Tools. EE19D – 25/01/2005. Topic. Definitions Visual Introduction of VHDL using EVITA ( www.aldec.com ) Getting started with Xilinx ISE Tool Simulation of VHDL Models with Moldelsim. Definition of an HDL.

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Studio Session 1: Introduction to VHDL and related Tools

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Studio session 1 introduction to vhdl and related tools

Studio Session 1: Introduction to VHDL and related Tools

EE19D – 25/01/2005


Topic

Topic

  • Definitions

  • Visual Introduction of VHDL using EVITA (www.aldec.com)

  • Getting started with Xilinx ISE Tool

  • Simulation of VHDL Models with Moldelsim


Definition of an hdl

Definition of an HDL

  • Def: A high level programming language used to model hardware.

    • special hardware related constructs

    • digital (now) and analog (near future)

    • models used for documentation, simulation, synthesis, and test generation

    • have been extended to the system design level


Language semantics

Language Semantics

  • Semantics: what is the meaning of a language construct?

  • HDLs have different semantics for different applications:

    • Simulation

    • Synthesis

    • Test

  • In this course we will be concerned with simulation and synthesis semantics.


Studio session 1 introduction to vhdl and related tools

VHDL

  • VHDL = VHSIC Hardware Description Language

  • VHSIC = Very High Speed Integrated Circuit Program

  • DOD began development in 1983

    • design exchange among VHSIC contractors

    • document parts with long functional life

  • IEEE Standardization

    • Standardization process began in 1985

    • IEEE Standard 1076 in 1987

    • Updated in 1993


Significance of vhdl

Significance of VHDL

  • VHDL provides a text based approach to structured hardware modeling and design.

  • Analogous to high level software languages such as PASCAL, C, C++, and JAVA.

  • An important tool in managing the complexity of VLSI systems.


Why use vhdl

Why Use VHDL?

  • Reason #1: it allows textual design representation

  • Reason #2: Ability to model at different levels of abstraction


Studio session 1 introduction to vhdl and related tools

SYSTEM

CHIP

REGISTER

GATE

CIRCUIT

SILICON

Abstraction Levels


Studio session 1 introduction to vhdl and related tools

SILICON LEVEL


Studio session 1 introduction to vhdl and related tools

V+

S

G

P

D

D

G

Vout

Vin

N

S

CIRCUIT LEVEL

Inverter


Studio session 1 introduction to vhdl and related tools

S

Q

Q

R

Q

S

R

Q

GATE LEVEL

Flip Flop


Studio session 1 introduction to vhdl and related tools

Select

REG

MUX

REG

CLK A

CLK B

INC

REGISTER LEVEL


Studio session 1 introduction to vhdl and related tools

CHIP LEVEL

RAM

µ

8

8

P

Par.

Port

8

USART

Int.

Con.


Studio session 1 introduction to vhdl and related tools

SYSTEM LEVEL

IMU

A/B

Computer

RADAR

C/D


Studio session 1 introduction to vhdl and related tools

  • VHDL Provides total modeling capability at the gate level, register level, and chip level.

  • It can also be used in many applications at the:

    • system level

    • circuit level

    • Switch level (gate-circuit hybrid)


Studio session 1 introduction to vhdl and related tools

Structural

Decomposition

Reason #3: Design Decomposition

VHDL supports very naturally the Design Decomposition process.

behavioral

model


Studio session 1 introduction to vhdl and related tools

Reason #4: Design Validation

  • VHDL can be used to validate design at a high level, thus detecting errors early in the design process

  • Important, because finding errors later is expensive


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