EE 241 Design Problem

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# EE 241 Design Problem - PowerPoint PPT Presentation

EE 241 Design Problem. Paguio , Cindy Sandoval, Andrew Valdez, Rozelle. Specifications. Typical Lab Supply Single Output Flyback converter in DCM Vi = universal supply (85V to 264V) Io = 0 to 3A Vo = 2V to 20V. Block Diagram. Linear Regulator. Flyback Converter. Assumptions:

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### EE 241 Design Problem

Paguio, Cindy

Sandoval, Andrew

Valdez, Rozelle

Specifications
• Typical Lab Supply
• Single Output
• Flyback converter in DCM
• Vi = universal supply (85V to 264V)
• Io = 0 to 3A
• Vo = 2V to 20V
Flyback Converter
• Assumptions:
• Efficiency = 80%
• fs = 175kHz
• Iout = 5A
• Design Approach
• 5 Outputs (4.3V, 8.3V, 12.3V, 16.3V, 20.3V)
• Tap Configuration
• 15V Primary Auxiliary Output
• To power PWM Controller
• 24V Secondary Auxiliary Output
• To power op-amps in linear regulator and the flyback switcher
Flyback Transformer Design
• Primary Side:
• Core: E14-3C90
• Ie = 78.6mm, Ae = 97.1mm^2, Ue =67

(1)

N = 26.68 turns

• Secondary Side:

(2)

15V flyback auxiliary output: Nsec = 3.48 turns

24V flyback auxiliary output: Nsec = 4.93 turns

Flyback Transformer
• Secondary Side:
• Multi-output tap configuration
• Outputs are in 4V increments (4.3V, 8.3V, 12.3V, 16.3V, 20.3V)
• Eq. 2 is used to get Nsec for Vout = 4.3V
• Nsec(4.3V) = 0.998 turns
• Nsec(4V) = 0.938 turns
• Nsec(8.3V) = Nsec(4.3V) + Nsec(4V)
• Nsec(12.3V) = Nsec(4.3V) + 2*Nsec(4V)
• Nsec(16.3V) = Nsec(4.3V) + 3*Nsec(4V)
• Nsec(20.3V) = Nsec(4.3V) + 4*Nsec(4V)
Flyback Transformer
• PWM Controller Circuit and Switch:
• Osc pin:
• fs = 175kHz, 1.8/RC, R >= 5kHz
• R1 = 5kohms, C4 = 2nF
• Sense pin:
• Pout = Vout,max*Iout,max = 20.3*5A=101.5W
• I_peak = (5.5*Pout)/Vin,min = (5.5*101.5)/(85*sqrt(2))

= 4.64A

• Rsense = 1.0/I_peak = 1.0/4.64 = 215mΩ
Flyback (Simulation)
• Conditions: Vin = 85Vrms
Flyback (Simulation)
• Conditions: Vin = 85Vrms