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Digital Fields Board (DFB) FPGA. Ken Stevens University of Colorado - LASP. Presentation Overview. Design Context Requirements Changes/Trades since PDR Module-level Design Examples FPGA Verification and Validation Strategy Current Status. DFB Block Diagram.

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Digital fields board dfb fpga

Digital Fields Board (DFB)FPGA

Ken Stevens

University of Colorado - LASP


Presentation overview
Presentation Overview

Design Context

Requirements

Changes/Trades since PDR

Module-level Design Examples

FPGA Verification and Validation Strategy

Current Status





FPGA Top-level: Block Diagram

Backplane Interface

Analog Muxes and ADCs

SRAM #1

SRAM #2


FPGA Top-level: THEMIS Heritage

Backplane Interface

Analog Muxes and ADCs

SRAM #1

SRAM #2


FPGA Top-level: Changes Since PDR

Backplane Interface

Analog Muxes and ADCs

SRAM #1

SRAM #2


FPGA Top-level: Implementation Status

Backplane Interface

Analog Muxes and ADCs

SRAM #1

SRAM #2


Fpga functional overview 1 3
FPGA Functional Overview (1/3)

  • The DFB FPGA accepts commands and provides telemetry to the DCB over a digital backplane:

    • Command Controller:

      • Decodes backplane protocol: ‘1’ start bit, 8-bit command ID, 16-bit command data field, odd parity bit, ‘0’ stop bit

      • Performs command translation to create appropriate register read/writes from/to sub-modules.

    • Data Controller:

      • Aligns telemetry data to increments of 1/128 second aligned to the 1 pps signal

      • Assigns APIDs

      • Encodes ALU data products for backplane transport to the DCB using a synchronous UART interface: ‘1’ start bit, 8-bit APID, 16-bit data field, odd parity bit, ‘0’ stop bit


Fpga functional overview 2 3
FPGA Functional Overview (2/3)

  • The DFB FPGA controls acquisition of the analog signals and converts them to a database of signals at various rates for further processing:

    • Analog to Digital Conversion

      • 16-bit resolution

      • 16.384 kS/s (214) sample rate

      • Cross-strapped ADCs for limited redundancy

    • Field Alignment

      • Rotates E and SCM values into the coordinate system of the DC magnetic field

    • Digital Filtering

      • Multi-tap FIR low-pass filter that creates output rates from the sampling rate down to 1/(214)x sampling rate…i.e. [16.384kS/s, 8.192kS/s, … 2S/s, 1S/s]

      • Band-pass filter taps available for trigger value calculations


Fpga functional overview 3 3
FPGA Functional Overview (3/3)

The DFB FPGA generates the following types of data in order to meet science requirements (configured by the DCB):

Trigger Data:

pseudo-power in 7 or 13 frequency bands in the range of 0 to 8kHz

Any two EDC, EAC, or SCM values

Time Series (Waveform) Data:

Reporting rates from 1s/s – 16Ks/s:

V1-V6, V1AC-V6AC, E12DC-E56DC, E12AC-E56AC, FM1-FM3, SCM1-SCM3

Spectra Data:

2048-point FFT with selectable frequency binning and time averaging

Any eight signals except V1-V6

Cross Spectral Data:

Selectable frequency binning and time averaging

Any four pairs from spectra data

Solitary Wave Detector Data:

Counts peaks and bins them according to magnitude

E12AC or E34AC


Implementation approach
Implementation Approach

General Approach

Using an FPGA-based implementation allows hardware to be tailored to the mission requirements

Lower power than an equivalent processor based DSP design

Heritage from THEMIS

LTC1604 ADC and ADC support circuitry

Digital Signal Processing algorithms

Backplane interface protocols

Changes and Improvements from THEMIS

Higher sample rates (16ks/s)

Addition of onboard Cross Spectral Analysis and Solitary Wave Detection

Use of a single RTAX2000 FPGA instead of three SX72 FPGAs

Rewrite of FPGA VHDL code

Higher performance implementation of DSP algorithms

Utilization of RTAX internal RAM to improve data flow and performance

Parameterization of all modules to accommodate unforeseen design changes

Standardization of all internal interconnect buses to Wishbone architecture


Trades changes since pdr
Trades & Changes Since PDR

Added circuitry and an additional external SRAM to provide synchronization of data transfer to the 1 pps signal…

Why? …to align data to increments of 1/128 second (the period of the buffer swapping in the DCB) coincident with the 1 pps signal so that DCB can correctly buffer and time-tag the data.

How? …added double buffers in the data controller that are capable of holding 1/128 of a second of data. Data is tagged at acquisition and placed in the appropriate FIFO depending on when the sample was taken. Latency through the DSP is less than 1/128 second for all data types. Data is then burst onto the backplane at the next 1/128 second marker.

Currently implemented and is in use in the lab using internal FPGA RAM but cannot hold the full data rate of 4096 words per 1/128 second period. An additional external SRAM has been added to the next board layout to facilitate 4096 word buffers for full rate data.


Module level design examples
Module-level Design Examples

Triggers and Waveforms are included only as backup slides since they were presented at PDR.

Spectra/X-spectra illustrated to give an idea of the steps in the design process.

Solitary Wave Detector to illustrate a “single page” overview.


Spectra/X-Spectra Data Path

Backplane Interface

Analog Muxes and ADCs

SRAM

SRAM


Spectra x spectra functional diagram
Spectra/X-Spectra Functional Diagram

FFT Generation:

- Select Input Signal and create 2048-point buffer

- Hanning Window

- Perform 2048-point FFT using Radix-2 Algorithm

- End up with 1024 Real and 1024 Imag points

Spectra Power:

- Calculate power by adding squares of Real and Imag

- Perform frequency binning

- Accumulate in time

- Pseudo log compress

- Report at selected cadence

X-Spectra:

- Calculate X-Spectra components (see diagram)

- Perform frequency binning

- Accumulate in time

- Pseudo log compress

- Report at selected cadence



Spectra x spectra design partitioning
Spectra/X-Spectra Design Partitioning

Control registers:

Implemented in the top-level module

Uses Wishbone interface

Ingress Processor

Compares incoming data from the digital filters with the selection registers and creates a 2048 sample buffer in external RAM for each enabled quantity

Notifies the Control State Machine when input buffers are available

Control State Machine (CSM)

When an input buffer is available, the CSM transfers the data from the external RAM to an internal RAM, manages the calculation of a spectra, and then transfers the results back into external RAM.

When the spectra calculations are complete, the CSM checks to see if any X-Spectra are enabled. If so, then the appropriate spectra are transferred to internal RAM, the CSM manages the calculation of the X-Spectra, and then transfers the results back to external RAM.


Spectra x spectra design partitioning1
Spectra/X-Spectra Design Partitioning

Arithmetic Logic Unit

Implements the arithmetic logic required to do Windowing, FFT, Unpacking, Power Calculation, and X-Spectral analysis…will show data flow for each of these operations shortly

Performs frequency binning

Performs time averaging

Egress Processor

Transfers spectra and x-spectra results from external RAM

Performs 34 to 8 pseudo-log compression

Transmits data to the telemetry stream at the appropriate cadence.


Spectra x spectra alu
Spectra/X-Spectra ALU

Spectra/X-Spectra ALU is 32-bit fixed-point with appropriate rounding.


Spectra x spectra alu hanning window
Spectra/X-Spectra ALU: Hanning Window

…other operations are included in the back-up slides.


Solitary Wave Detector Data Path

Backplane Interface

Analog Muxes and ADCs

SRAM

SRAM


Solitary Wave Detector

  • Detect and Count Solitary Waves

  • Algorithm Overview:

    • Collect data samples in a buffer of 32, 64,128, or 256 samples

    • Calculate

    • The average is calculated and subtracted from each sample in the buffer to normalize the data.

    • If the highest absolute value in the buffer is more than 4X greater than pRMS, then count the peak as a solitary wave event

    • Events are counted in one of four counters based on software programmable threshold values

    • Reporting period is selectable from 0.5s to 32s in 0.5s increments

    • At the end of the reporting period, the four count values are pseudo-log compressed from 12 bits to 8 bits and sent to the TM module


Fpga verification approach
FPGA Verification Approach

Verification is performed independent of design

Verification performed at both the module & chip levels

Functionality and algorithm correctness is verified through module-level simulation

Interaction with other parts of the system is verified through chip-level simulation

Assertion Based Verification (ABV)

Using Active HDL

Code Coverage used to quantify verification

Using Active HDL





FPGA Validation Plan

Signal into DFB Analog Electronics

From ADC to FPGA

FPGA processing

FPGA output

Compare FPGA, Simulation & IDL results

Record (raw) waveforms at 16kHz

IDL routines performing same tasks as FPGA

IDL formatting of data for ALU module simulation

FPGA Simulation


Configuration Validation Plan

  • Verify commanding functionality

    • Start by testing nominal / default configuration

    • Can not test every possible configuration

    • (thousands for filter banks alone)

    • Instead, test each configuration option fully, one at a time (31 possible for filter banks)


Configuration Validation Plan

S1(10) S2(10) Speed(11) En (2) En(2) Bands(2)

E12 DC

E12 DC

1/16 S/s

On

On

7 bins

E34 DC

E34 DC

1/8 S/s

Off

Off

13 bins

E56 DC

E56 DC

1/4 S/s

SCM3

SCM3

64 S/s


Configuration Validation Plan

E12 DC

7 bins

On

On

1/8 S/s

E34 DC

S1(10) S2(10) Speed(11) En (2) En(2) Bands(2)

E12 DC

1/16 S/s

E34 DC

Off

Off

13 bins

E56 DC

E56 DC

1/4 S/s

SCM3

SCM3

64 S/s


Configuration Validation Plan

E12 DC

E34 DC

E56 DC

SCM3

7 bins

On

E34 DC

On

1/8 S/s

S1(10) S2(10) Speed(11) En (2) En(2) Bands(2)

E12 DC

1/16 S/s

Off

Off

13 bins

E56 DC

1/4 S/s

SCM3

64 S/s



Dfb fpga design process
DFB FPGA: Design Process

ETU 1&2: Used to verify algorithms and functionality

Reprogrammable FPGAs – ProASIC3e

1xSRAM to implement either FFT or 1 PPS in external RAM

Currently in use at LASP and Berkeley

ETU 3: Used to verify flight board layout and AX/RTAX specific logic

Add EDAC RAMs where appropriate

AX2000 in a BGA package with adapter to flight pin pattern

2x SRAM to implement both FFT and 1 PPS in external RAM

FPGA to verify flight board characteristics at end of October

FM1: Implements flight functionality

Pinout change because of BGA to QFP adapter used on ETU 3

Flight functionality at end of 2009


Key Implementation Guidelines

  • Specification

    • Digital Fields Board Specification (RBSP_EFW_DFB_001D_SPEC Rev D)

    • Digital Fields Board FPGA Specification – In Progress

  • Coding Standards

    • LASP FPGA Design Guide

    • NASA 500-PG-8700.2.8

    • Actel HDL coding Style Guide

    • Single clock domain

    • Fully synchronous design

    • Power-on reset is asynchronously applied, synchronously cleared

    • Scripts used for running simulations and builds to ensure consistency

  • Version Control

    • All source code, design documents, and test files are version controlled using Subversion

    • Major releases are archived in Agile CM system



Current status
Current Status

  • Peer review completed 9/10/09. Actions and responses are included in backup slides.

  • Working on algorithmic verification of spectra/x-spectra and solitary wave detector.

  • Using waveform and trigger functions in the lab to validate board layout, etc.

  • Expect ETU3 functional at end of October, FM1 at end of 2009



Efw dfb peer review sept 10 2009
EFW DFB Peer ReviewSept 10, 2009


Efw dfb peer review action item summary 1of2
EFW – DFB Peer Review Action Item Summary (1of2)


Efw dfb peer review action item summary 2of2
EFW – DFB Peer Review Action Item Summary (2of2)


DFB FPGA: Field Alignment Flow Diagram

E12,34,56

B (from FGM)

Adjust Gains, Offsets

Offsets

5-minute lowpass

filter to find offsets

Adjust gain/offset

Rotation

matrix

Gains

Offsets (from

ground)

Rotate to E system

(gains included)

Adjust gain/offset

Interpolate

Rotate E, B simultaneously

in the xy plane until Bx = 0.

Perform rotations

using CORDIC

Rotate E, B simultaneously

in the xz plane until Bz = 0.

E_perp = Ey/1.646

E_par = Ex/1.6462


DFB FPGA: Digital Filters

  • Uses a cascading filter algorithm that allows generation of both low-pass and band-pass outputs.

  • Each filter bank requires about the same processing as 2 comparable filters (e.g. 5th order Bessel).

  • Since quantities are typically filtered to so many different rates, and since some quantities require a filter bank anyway, this approach saves complexity and power.

  • -3dB point = 0.6 fNyquist

  • Power at fNyquist= -12 dB

  • Rolloff ~ 25 dB/octave

  • No phase shift


DFB FPGA: Triggers

  • Selects appropriate band-pass filter value from the digital filters output

  • The power in a particular band is approximated by averaging the absolute value

  • The results are used mainly in triggering algorithms


DFB FPGA: Digital Filters Diagram

Low pass section

Bandpass section

8 kS/s

+

-

Shift Z-3

7-tap FIR filter

2-4 kHz

Averager

4 kS/s

2:1 Decimating FIR filter (3-tap)

+

-

Shift Z-3

7-tap FIR filter

1-2 kHz

Averager

2 kS/s

2:1 Decimating FIR filter (3-tap)

(9 more banks)

(9 more banks)

+

-

Shift Z-3

7-tap FIR filter

1-2 Hz

Averager

2 S/s

2:1 Decimating FIR filter (3-tap)








Dfb fpga spectra alu code example 1 3
DFB FPGA: Spectra ALU Code Example 1/3

Define the number of clock cycles required for the operation…controls counters, etc…

-- define the number of cycles required for each operation for

-- stage 1, stage 2, and egress stage

constant CYCLES : natural_array_2d :=

((1,1,1), -- WINDOW

(4,6,4), -- FFT

(4,4,4), -- UNPACK1

(4,6,4), -- UNPACK

(2,2,1), -- POWER

(4,4,2)); -- XSPECTRA


Dfb fpga spectra alu code example 2 3
DFB FPGA: Spectra ALU Code Example 2/3

2. Define the control points in the flow diagrams and assign them according to the operation desired…

-- define the control points for stage #1 for each iteration of each operation:

-- the control points are notated in the alu data flow diagrams in the implementation specification

-- the order is...(mux0, mux1, mux2, mux3, mux4, addsub5, egress_ff_select6)

constant S1_CTRL : natural_array_3d :=

(((0,0,1,0,1,0,2),(0,0,0,0,0,0,0),(0,0,0,0,0,0,0),(0,0,0,0,0,0,0),(0,0,0,0,0,0,0),(0,0,0,0,0,0,0)), -- WINDOW

((0,0,0,0,0,0,0),(1,0,0,0,0,0,1),(2,0,2,0,1,0,2),(2,0,3,0,1,0,3),(3,0,2,0,1,0,4),(3,0,3,0,1,0,5)), -- FFT

((0,0,0,0,0,0,0),(1,0,0,0,0,0,1),(2,0,0,0,0,0,2),(3,0,0,0,0,0,4),(0,0,0,0,0,0,0),(0,0,0,0,0,0,0)), -- UNPACK1

((0,2,0,1,0,0,0),(1,3,0,1,0,1,1),(1,3,2,1,1,0,2),(1,3,3,1,1,0,3),(0,2,2,1,1,1,4),(0,2,3,1,1,1,5)), -- UNPACK

((0,0,0,0,1,0,2),(1,1,0,0,1,0,3),(0,0,0,0,0,0,0),(0,0,0,0,0,0,0),(0,0,0,0,0,0,0),(0,0,0,0,0,0,0)), -- POWER

((0,2,0,0,1,0,2),(1,3,0,0,1,0,3),(2,1,0,0,1,0,4),(0,3,0,0,1,0,5),(0,0,0,0,0,0,0),(0,0,0,0,0,0,0))); -- XSPECTRA

-- define the control points for stage #2 for each iteration of the each operation:

-- the control points are notated in the alu data flow diagrams in the implementation specification

-- the order is...(mux0, mux1, mux2, mux3, addsub4, addsub5, egress_ff_select6)

constant S2_CTRL : natural_array_3d :=

(((2,0,0,0,0,0,0),(0,0,0,0,0,0,0),(0,0,0,0,0,0,0),(0,0,0,0,0,0,0)), -- WINDOW

((0,2,5,1,1,0,0),(1,3,4,1,0,0,1),(0,2,5,1,1,1,2),(1,3,4,1,0,1,3)), -- FFT

((0,0,1,2,0,0,0),(0,0,0,3,0,0,1),(2,0,0,0,0,0,2),(4,0,0,0,0,0,3)), -- UNPACK1

((0,2,5,1,1,0,0),(1,3,4,1,0,0,1),(0,2,5,1,1,1,2),(1,3,4,1,0,1,3)), -- UNPACK

((0,2,3,2,0,0,0),(0,0,0,0,0,0,0),(0,0,0,0,0,0,0),(0,0,0,0,0,0,0)), -- POWER

((0,2,3,2,0,0,0),(0,4,5,2,1,0,1),(0,0,0,0,0,0,0),(0,0,0,0,0,0,0))); -- XSPECTRA


Dfb fpga spectra alu code example 3 3
DFB FPGA: Spectra ALU Code Example 3/3

3. Implement the actual arithmetic logic using the control points…

-- stage 1 arithmetic logic ---------------------------------------------------

s1_mux0_dout <= s1sm.iff.reg(S1_CTRL(s1sm.iff.aop,s1sm.ctr,0));

s1_mux1_dout <= s1sm.iff.reg(S1_CTRL(s1sm.iff.aop,s1sm.ctr,1));

s1_mux2_dout <= s1_mux1_dout(31 downto 16) when S1_CTRL(s1sm.iff.aop,s1sm.ctr,2) = 0 else

s1sm.iff.win when S1_CTRL(s1sm.iff.aop,s1sm.ctr,2) = 1 else

s1sm.iff.cos when S1_CTRL(s1sm.iff.aop,s1sm.ctr,2) = 2 else

s1sm.iff.sin;

s1_mux3_dout <= s1_mux0_dout when S1_CTRL(s1sm.iff.aop,s1sm.ctr,3) = 0 else s1_unpack_dout;

s1_mux4_dout <= s1_mux3_dout when S1_CTRL(s1sm.iff.aop,s1sm.ctr,4) = 0 else s1_mult_dout;

s1_unpack_dout <= (s1_mux0_dout+s1_mux1_dout)/2 when S1_CTRL(s1sm.iff.aop,s1sm.ctr,5) = 0 else

(s1_mux0_dout-s1_mux1_dout)/2;

s1_mult_dout_temp <= s1_mux3_dout*s1_mux2_dout;

s1_mult_dout <= s1_mult_dout_temp(DAT_WIDTH+SINCOS_WIDTH-1 downto SINCOS_WIDTH);

-- stage 2 arithmetic logic ---------------------------------------------------

s2_mux1_dout <= s2sm.iff.reg(S2_CTRL(s2sm.iff.aop,s2sm.ctr,0));

s2_mux2_dout <= s2sm.iff.reg(S2_CTRL(s2sm.iff.aop,s2sm.ctr,1));

s2_mux3_dout <= s2sm.iff.reg(S2_CTRL(s2sm.iff.aop,s2sm.ctr,2));

s2_mux4_dout <= s2_mux1_dout when S2_CTRL(s2sm.iff.aop,s2sm.ctr,3) = 0 else

s2_add2_dout when S2_CTRL(s2sm.iff.aop,s2sm.ctr,3) = 1 else

s2_add1_dout when S2_CTRL(s2sm.iff.aop,s2sm.ctr,3) = 2 else

(others => '0');

s2_add1_dout <= s2_mux2_dout+s2_mux3_dout when S2_CTRL(s2sm.iff.aop,s2sm.ctr,4) = 0 else

s2_mux2_dout-s2_mux3_dout;

s2_add2_dout <= s2_mux1_dout+s2_add1_dout when S2_CTRL(s2sm.iff.aop,s2sm.ctr,5) = 0 else

s2_mux1_dout-s2_add1_dout;



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