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CS151B Computer Systems Architecture Winter 2002 TuTh 2-4pm - 2444 BH

CS151B Computer Systems Architecture Winter 2002 TuTh 2-4pm - 2444 BH. Lecture 7 Designing a Single Cycle Datapath. Instructor: Prof. Jason Cong <cong@cs.ucla.edu>. Review: DIVIDE HARDWARE Version 3. 32-bit Divisor reg, 32 -bit ALU, 64-bit Remainder reg, ( 0 -bit Quotient reg). Divisor.

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CS151B Computer Systems Architecture Winter 2002 TuTh 2-4pm - 2444 BH

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  1. CS151BComputer Systems ArchitectureWinter 2002 TuTh 2-4pm - 2444 BH Lecture 7 Designing a Single Cycle Datapath Instructor: Prof. Jason Cong <cong@cs.ucla.edu>

  2. Review: DIVIDE HARDWARE Version 3 • 32-bit Divisor reg, 32 -bit ALU, 64-bit Remainder reg, (0-bit Quotient reg) Divisor 32 bits 32-bit ALU “HI” “LO” Shift Left (Quotient) Remainder Control Write 64 bits • Multiplication and Division can use same hardware! Jason Cong

  3. Review: Recall Scientific Notation exponent decimal point Sign, magnitude • Issues: • Arithmetic (+, -, *, / ) • Representation, Normal form • Range and Precision • Rounding • Exceptions (e.g., divide by zero, overflow, underflow) • Errors • Properties ( negation, inversion, if A  B then A - B  0 ) 23 -24 6.02 x 10 1.673 x 10 radix (base) Mantissa Sign, magnitude e - 127 IEEE F.P. ± 1.M x 2 Jason Cong

  4. Review from Prerequisties: Floating-Point Arithmetic Representation of floating point numbers in IEEE 754 standard: single precision 1 8 23 S E sign M mantissa: sign + magnitude, normalized binary significand w/ hidden integer bit: 1.M exponent: excess 127 binary integer actual exponent is e = E - 127 0 < E < 255 S E-127 N = (-1) 2 (1.M) 0 = 0 00000000 0 . . . 0 -1.5 = 1 01111111 10 . . . 0 Magnitude of numbers that can be represented is in the range: -126 127 -23 ) 2 (1.0) (2 - 2 to 2 which is approximately: -38 38 to 3.40 x 10 1.8 x 10 (integer comparison valid on IEEE Fl.Pt. numbers of same sign!) Jason Cong

  5. Basic Addition Algorithm/Multiply issues For addition (or subtraction) this translates into the following steps: (1) compute Ye - Xe (getting ready to align binary point) (2) right shift Xm that many positions to form Xm 2 (3) compute Xm 2 + Ym if representation demands normalization, then normalization step follows: (4) left shift result, decrement result exponent (e.g., 0.001xx…) right shift result, increment result exponent (e.g., 101.1xx…) continue until MSB of data is 1 (NOTE: Hidden bit in IEEE Standard) (5) for multiply, doubly biased exponent must be corrected: Xe = 7 Ye = -3 Excess 8 extra subtraction step of the bias amount (6) if result is 0 mantissa, may need to zero exponent by special step Xe-Ye Xe-Ye = 7 + 8 = -3 + 8 4 + 8 + 8 Xe = 1111 Ye = 0101 10100 = 15 = 5 20 Jason Cong

  6. Processor Input Control Memory Datapath Output The Big Picture: Where are We Now? • The Five Classic Components of a Computer • What we covered so far • Instruction set • Performance metrics • Arithmetic logic • Today’s Topic: Design a Single Cycle Processor Jason Cong

  7. CPI Inst. Count Cycle Time The Big Picture: The Performance Perspective • Performance of a machine is determined by: • Instruction count • Clock cycle time • Clock cycles per instruction • Processor design (datapath and control) will determine: • Clock cycle time • Clock cycles per instruction • Today: • Single cycle processor: • Advantage: One clock cycle per instruction • Disadvantage: long cycle time Jason Cong

  8. How to Design a Processor: step-by-step • 1. Analyze instruction set => datapath requirements • the meaning of each instruction is given by the register transfers • datapath must include storage element for ISA registers • possibly more • datapath must support each register transfer • 2. Select set of datapath components and establish clocking methodology • 3. Assemble datapath meeting the requirements • 4. Analyze implementation of each instruction to determine setting of control points that effects the register transfer. • 5. Assemble the control logic Jason Cong

  9. 31 26 21 16 11 6 0 op rs rt rd shamt funct 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits 31 26 21 16 0 immediate op rs rt 6 bits 5 bits 5 bits 16 bits 31 26 0 op target address 6 bits 26 bits The MIPS Instruction Formats • All MIPS instructions are 32 bits long. The three instruction formats: • R-type • I-type • J-type • The different fields are: • op: operation of the instruction • rs, rt, rd: the source and destination register specifiers • shamt: shift amount • funct: selects the variant of the operation in the “op” field • address / immediate: address offset or immediate value • target address: target address of the jump instruction Jason Cong

  10. 31 26 21 16 11 6 0 op rs rt rd shamt funct 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits 31 26 21 16 0 op rs rt immediate 6 bits 5 bits 5 bits 16 bits 31 26 21 16 0 op rs rt immediate 6 bits 5 bits 5 bits 16 bits 31 26 21 16 0 op rs rt immediate 6 bits 5 bits 5 bits 16 bits Step 1a: The MIPS-lite Subset for today • ADD and SUB • addU rd, rs, rt • subU rd, rs, rt • OR Immediate: • ori rt, rs, imm16 • LOAD and STORE Word • lw rt, rs, imm16 • sw rt, rs, imm16 • BRANCH: • beq rs, rt, imm16 Jason Cong

  11. Register Transfer Level Description • RTL gives the meaning of the instructions • All start by fetching the instruction op | rs | rt | rd | shamt | funct = MEM[ PC ] op | rs | rt | Imm16 = MEM[ PC ] inst Register Transfers ADDU R[rd] <– R[rs] + R[rt]; PC <– PC + 4 SUBU R[rd] <– R[rs] – R[rt]; PC <– PC + 4 ORi R[rt] <– R[rs] | zero_ext(Imm16); PC <– PC + 4 LOAD R[rt] <– MEM[ R[rs] + sign_ext(Imm16)]; PC <– PC + 4 STORE MEM[ R[rs] + sign_ext(Imm16) ] <– R[rt]; PC <– PC + 4 BEQ if ( R[rs] == R[rt] ) then PC <– PC + 4 + sign_ext(Imm16)] || 00 else PC <– PC + 4 Jason Cong

  12. Step 1: Requirements of the Instruction Set • Memory • instruction & data • Registers (32 x 32) • read RS • read RT • Write RT or RD • PC • Extender • Add and Sub register or extended immediate • Add 4 or extended immediate to PC Jason Cong

  13. Step 2: Components of the Datapath • Combinational Elements • Storage Elements • Clocking methodology Jason Cong

  14. Combinational Logic Elements (Basic Building Blocks) CarryIn A 32 • Adder • MUX • ALU Sum Adder 32 B Carry 32 Select A 32 Y MUX 32 B 32 OP A 32 Result ALU 32 B 32 Jason Cong

  15. Storage Element: Register (Basic Building Block) Write Enable • Register • Similar to the D Flip Flop except • N-bit input and output • Write Enable input • Write Enable: • negated (0): Data Out will not change • asserted (1): Data Out will become Data In (at the falling edge of the clock) Data In Data Out N N Clk Jason Cong

  16. Storage Element: Register File RW RA RB Write Enable 5 5 5 • Register File consists of 32 registers: • Two 32-bit output busses: busA and busB • One 32-bit input bus: busW • Register is selected by: • RA (number) selects the register to put on busA (data) • RB (number) selects the register to put on busB (data) • RW (number) selects the register to be writtenvia busW (data) when Write Enable is 1 • Clock input (CLK) • The CLK input is a factor ONLY during write operation • During read operation, behaves as a combinational logic block: • RA or RB valid => busA or busB valid after “access time.” busA busW 32 32 32-bit Registers 32 busB Clk 32 Jason Cong

  17. Storage Element: Idealized Memory Write Enable Address • Memory (idealized) • One input bus: Data In • One output bus: Data Out • Memory word is selected by: • Address selects the word to put on Data Out • Write Enable = 1: address selects the memoryword to be written via the Data In bus • Clock input (CLK) • The CLK input is a factor ONLY during write operation • During read operation, behaves as a combinational logic block: • Address valid => Data Out valid after “access time.” Data In DataOut 32 32 Clk Jason Cong

  18. . . . . . . . . . . . . Clocking Methodology Clk Setup Hold Setup Hold • All storage elements are clocked by the same clock edge • Cycle Time = CLK-to-Q + Longest Delay Path + Setup + Clock Skew • To avoid race condition • (CLK-to-Q + Shortest Delay Path - Clock Skew) > Hold Time Don’t Care Jason Cong

  19. Step 3: Assemble DataPath meeting our requirements • Register Transfer Requirements Datapath Assembly • Instruction Fetch • Read Operands and Execute Operation Jason Cong

  20. Next Address Logic Address Instruction Memory 3a: Overview of the Instruction Fetch Unit • The common RTL operations • Fetch the Instruction: mem[PC] • Update the program counter: • Sequential Code: PC <- PC + 4 • Branch and Jump: PC <- “something else” Clk PC Instruction Word 32 Jason Cong

  21. 31 26 21 16 11 6 0 op rs rt rd shamt funct 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits 3b: Add & Subtract • R[rd] <- R[rs] op R[rt] Example: addU rd, rs, rt • Ra, Rb, and Rw come from instruction’s rs, rt, and rd fields • ALUctr and RegWr: control logic after decoding the instruction Rd Rs Rt ALUctr RegWr 5 5 5 busA Rw Ra Rb busW 32 Result 32 32-bit Registers ALU 32 32 busB Clk 32 Jason Cong

  22. Register-Register Timing: One complete cycle Clk Clk-to-Q Old Value New Value PC Instruction Memory Access Time Rs, Rt, Rd, Op, Func Old Value New Value Delay through Control Logic ALUctr Old Value New Value RegWr Old Value New Value Register File Access Time busA, B Old Value New Value ALU Delay busW Old Value New Value Rd Rs Rt ALUctr Register Write Occurs Here RegWr 5 5 5 busA Rw Ra Rb busW 32 Result 32 32-bit Registers ALU 32 32 busB Clk 32 Jason Cong

  23. 11 31 26 21 16 0 op rs rt immediate 6 bits 5 bits 5 bits 16 bits rd? 31 16 15 0 immediate 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 bits 16 bits Rd Rt RegDst Mux 3c: Logical Operations with Immediate • R[rt] <- R[rs] op ZeroExt[imm16] ] Rt? Rs ALUctr RegWr 5 5 5 busA Rw Ra Rb busW 32 Result 32 32-bit Registers ALU 32 32 busB Clk 32 Mux ZeroExt imm16 32 16 ALUSrc Jason Cong

  24. 11 31 26 21 16 0 op rs rt immediate 6 bits 5 bits 5 bits 16 bits rd 3d: Load Operations • R[rt] <- Mem[R[rs] + SignExt[imm16]] Example: lw rt, rs, imm16 Rd Rt RegDst Mux Rt? Rs ALUctr RegWr 5 5 5 busA W_Src Rw Ra Rb busW 32 32 32-bit Registers ALU 32 32 busB Clk MemWr 32 Mux Mux WrEn Adr Data In 32 ?? Data Memory Extender 32 imm16 32 16 Clk ALUSrc Jason Cong ExtOp

  25. 31 26 21 16 0 op rs rt immediate 6 bits 5 bits 5 bits 16 bits Rd Rt ALUctr MemWr W_Src RegDst Mux Rs Rt RegWr 5 5 5 busA Rw Ra Rb busW 32 32 32-bit Registers ALU 32 32 busB Clk 32 Mux Mux WrEn Adr Data In 32 32 Data Memory Extender imm16 32 16 Clk ALUSrc ExtOp 3e: Store Operations • Mem[ R[rs] + SignExt[imm16] <- R[rt] ] Example: sw rt, rs, imm16 Jason Cong

  26. 31 26 21 16 0 op rs rt immediate 6 bits 5 bits 5 bits 16 bits 3f: The Branch Instruction • beq rs, rt, imm16 • mem[PC] Fetch the instruction from memory • Equal <- R[rs] == R[rt] Calculate the branch condition • if (Equal) Calculate the next instruction’s address • PC <- PC + 4 + ( SignExt(imm16) x 4 ) • else • PC <- PC + 4 Jason Cong

  27. 31 26 21 16 0 op rs rt immediate 6 bits 5 bits 5 bits 16 bits Cond Rs Rt 4 RegWr 5 5 5 busA Adder Rw Ra Rb busW 32 32 32-bit Registers Equal? Mux PC busB Clk 32 Adder Clk Datapath for Branch Operations • beq rs, rt, imm16 Datapath generates condition (equal) Inst Address nPC_sel 32 00 imm16 PC Ext Jason Cong

  28. Inst Memory Adr Adder Mux Adder Putting it All Together: A Single Cycle Datapath Instruction<31:0> <21:25> <16:20> <11:15> <0:15> Rs Rt Rd Imm16 RegDst nPC_sel ALUctr MemWr MemtoReg Equal Rt Rd 0 1 Rs Rt 4 RegWr 5 5 5 busA Rw Ra Rb = busW 00 32 32 32-bit Registers ALU 0 32 busB 32 0 PC 32 Mux Mux Clk 32 WrEn Adr 1 1 Data In Extender Data Memory imm16 PC Ext 32 Clk 16 Clk imm16 ExtOp ALUSrc Jason Cong

  29. ALU PC Clk An Abstract View of the Critical Path • Register file and ideal memory: • The CLK input is a factor ONLY during write operation • During read operation, behave as combinational logic: • Address valid => Output valid after “access time.” Critical Path (Load Operation) = PC’s Clk-to-Q + Instruction Memory’s Access Time + Register File’s Access Time + ALU to Perform a 32-bit Add + Data Memory Access Time + Setup Time for Register File Write + Clock Skew Ideal Instruction Memory Instruction Rd Rs Rt Imm 5 5 5 16 Instruction Address A Data Address 32 Rw Ra Rb 32 Ideal Data Memory 32 32 32-bit Registers Next Address Data In B Clk Clk 32 Jason Cong

  30. ALU PC Clk An Abstract View of the Implementation Control Ideal Instruction Memory Control Signals Conditions Instruction Rd Rs Rt 5 5 5 Instruction Address A Data Address Data Out 32 Rw Ra Rb 32 Ideal Data Memory 32 32 32-bit Registers Next Address Data In B Clk Clk 32 Datapath Jason Cong

  31. Steps 4 & 5: Implement the control Next Time! Jason Cong

  32. Summary • 5 steps to design a processor • 1. Analyze instruction set => datapath requirements • 2. Select set of datapath components & establish clock methodology • 3. Assemble datapath meeting the requirements • 4. Analyze implementation of each instruction to determine setting of control points that effects the register transfer. • 5. Assemble the control logic • MIPS makes it easier • Instructions same size • Source registers always in same place • Immediates same size, location • Operations always on registers/immediates • Single cycle datapath => CPI=1, CCT => long • Next time: implementing control Jason Cong

  33. Acknowledgements • The majority of slides in this lecture are from UC Berkeley for their CS152 course (David Patterson, John Kubiatowicz, …) Jason Cong

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