QIE10 development. Nov. 7, 2011: The first full-chip prototype was submitted to MOSIS. Two previous prototype submissions were for the input amp/splitter and ADC sections. Both functioned as expected, so success is expected for this first full-chip prototype.
Nov. 7, 2011: The first full-chip prototype was submitted to MOSIS.
Two previous prototype submissions were for the input amp/splitter and ADC sections.
Both functioned as expected, so success is expected for this first full-chip prototype.
Output is 2-bit exponent (four ranges) and 6-bit mantissa (non-linear ADC).
LSB = 3fC, maximum input = 330 pC (approx. 17-bit dynamic range).
3 modes of operation: Normal, Program, and Charge Inject.
Both inverting and non-inverting inputs are available.
Separate Frontend (integration) and Backend (digital output) 40 MHz clock inputs.
Parallel LVDS digital outputs (mantissa, exponent, CapID, timing discriminator).
Programmable via shift register:
- Timing discriminator threshold
- Pedestal DAC
- Separate CapID pedestals on the lowest range
- Force to fixed range operation for testing
- Charge injection DAC (8 levels, covering 2 points on each of the 4 ranges)
- Input bias levels (allows adjusting input impedance, etc.)
and digital MUX
or Charge Inject)
Range Select and MUX
scaled by X8
LVDS outputs (6 bits mantissa, 2 bits exponent, 2 bits CapID)
Serial program shift register
Serial program in
Serial program out
Digital LVDS Inputs
(FEck, BEck, Reset)