Testing

1. Testing

2. Problems of Ideal Tests • Ideal tests detect all defects produced in the manufacturing process. • Ideal tests pass all functionally good devices. • Very large numbers and varieties of possible defects need to be tested. • Difficult to generate tests for some real defects. Defect-oriented testing is an open problem.

3. Real Tests • Based on analyzable fault models, which may not map on real defects. • Incomplete coverage of modeled faults due to high complexity. • Some good chips are rejected. The fraction (or percentage) of such chips is called the yield loss. • Some bad chips pass tests. The fraction (or percentage) of bad chips among all passing chips is called the defect level.

4. Testing as Filter Process Mostly good chips Good chips Prob(pass test) = high Prob(good) = y Prob(pass test) = low Fabricated chips Prob(fail test) = low Mostly bad chips Defective chips Prob(bad) = 1- y Prob(fail test) = high

5. Costs of Testing • Design for testability (DFT) • Chip area overhead and yield reduction • Performance overhead • Software processes of test • Test generation and fault simulation • Test programming and debugging • Manufacturing test • Automatic test equipment (ATE) capital cost • Test center operational cost

6. Int. bus Logic block A Logic block B PO PI Test input Test output Design for Testability (DFT) DFT refers to hardware design styles or added hardware that reduces test generation complexity. Motivation: Test generation complexity increases exponentially with the size of the circuit. Example: Test hardware applies tests to blocks A and B and to internal bus; avoids test generation for combined A and B blocks.

7. Cost of Manufacturing Testing in 2000AD • 0.5-1.0GHz, analog instruments,1,024 digital pins: ATE purchase price • = $1.2M + 1,024 x $3,000 = $4.272M • Running cost (five-year linear depreciation) • = Depreciation + Maintenance + Operation • = $0.854M + $0.085M + $0.5M • = $1.439M/year • Test cost (24 hour ATE operation) • = $1.439M/(365 x 24 x 3,600) • = 4.5 cents/second

8. Testing Principle

9. Automatic Test Equipment Components • Consists of: • Powerful computer • Powerful 32-bit Digital Signal Processor (DSP) for analog testing • Test Program (written in high-level language) running on the computer • Probe Head (actually touches the bare or packaged chip to perform fault detection experiments) • Probe Card or Membrane Probe (contains electronics to measure signals on chip pin or pad)

10. ADVANTEST Model T6682 ATE

11. T6682 ATE Block Diagram

12. LTX FUSION HF ATE

13. Verification Testing • Ferociously expensive • May comprise: • Scanning Electron Microscope tests • Bright-Lite detection of defects • Electron beam testing • Artificial intelligence (expert system) methods • Repeated functional tests

14. Characterization Test • Worst-case test • Choose test that passes/fails chips • Select statistically significant sample of chips • Repeat test for every combination of 2+ environmental variables • Plot results in Shmoo plot • Diagnose and correct design errors • Continue throughout production life of chips to improve design and process to increase yield

15. Manufacturing Test • Determines whether manufactured chip meets specs • Must cover high % of modeled faults • Must minimize test time (to control cost) • No fault diagnosis • Tests every device on chip • Test at speed of application or speed guaranteed by supplier

16. Burn-in or Stress Test • Process: • Subject chips to high temperature & over-voltage supply, while running production tests • Catches: • Infant mortality cases – these are damaged chips that will fail in the first 2 days of operation – causes bad devices to actually fail before chips are shipped to customers • Freak failures – devices having same failure mechanisms as reliable devices

17. Sub-types of Tests • Parametric – measures electrical properties of pin electronics – delay, voltages, currents, etc. – fast and cheap • Functional – used to cover very high % of modeled faults – test every transistor and wire in digital circuits – long and expensive – main topic of tutorial

18. Fault Modeling • Why model faults? • Some real defects in VLSI and PCB • Common fault models • Stuck-at faults • Single stuck-at faults • Fault equivalence • Fault dominance and checkpoint theorem • Classes of stuck-at faults and multiple faults • Transistor faults • Summary

19. Some Real Defects in Chips • Processing defects • Missing contact windows • Parasitic transistors • Oxide breakdown • . . . • Material defects • Bulk defects (cracks, crystal imperfections) • Surface impurities (ion migration) • . . . • Time-dependent failures • Dielectric breakdown • Electromigration • . . . • Packaging failures • Contact degradation • Seal leaks • . . . Ref.: M. J. Howes and D. V. Morgan, Reliability and Degradation - Semiconductor Devices and Circuits, Wiley, 1981.

20. Observed PCB Defects Occurrence frequency (%) 51 1 6 13 6 8 5 5 5 Defect classes Shorts Opens Missing components Wrong components Reversed components Bent leads Analog specifications Digital logic Performance (timing) Ref.: J. Bateson, In-Circuit Testing, Van Nostrand Reinhold, 1985.

21. Common Fault Models • Single stuck-at faults • Transistor open and short faults • Memory faults • PLA faults (stuck-at, cross-point, bridging) • Functional faults (processors) • Delay faults (transition, path) • Analog faults • etc.

22. Single Stuck-at Fault • Three properties define a single stuck-at fault • Only one line is faulty • The faulty line is permanently set to 0 or 1 • The fault can be at an input or output of a gate • Example: XOR circuit has 12 fault sites ( ) and 24 single stuck-at faults Faulty circuit value Good circuit value j c 0(1) s-a-0 d a 1(0) g h 1 z i 0 1 e b 1 k f Test vector for h s-a-0 fault

23. Fault Equivalence • Number of fault sites in a Boolean gate circuit = #PI + #gates + # (fanout branches). • Fault equivalence: Fault sets f1 and f2 are equivalent if all tests that detect f1 also detect f2 and vice versa. • If faults f1 and f2 are equivalent then the corresponding faulty functions are identical. • Fault collapsing: All single faults of a logic circuit can be divided into disjoint equivalence subsets, where all faults in a subset are mutually equivalent. A collapsed fault set contains one fault from each equivalence subset.

24. sa0 sa1 sa0 sa1 sa0 sa1 sa0 sa1 sa0 sa1 sa0 sa1 sa0 sa1 sa0 sa1 sa0 sa1 Equivalence Rules sa0 sa0 sa1 sa1 WIRE AND OR sa0 sa1 NOT sa0 sa1 sa0 sa1 sa0 sa1 sa0 NAND NOR sa1 sa0 sa0 sa1 sa1 sa0 sa1 FANOUT

25. Dominance Example sa0 sa1 Faults in red removed by equivalence collapsing sa0sa1 sa0 sa1 sa0 sa1 sa0 sa1 sa0 sa1 sa0 sa1 sa0sa1 sa0sa1 sa0 sa1 Faults in yellow removed by dominance collapsing sa0 sa1 sa0 sa1 sa0sa1 sa0 sa1 sa0sa1 sa0 sa1 15 Collapse ratio = ── = 0.47 32

26. Fault Dominance • If all tests of some fault F1 detect another fault F2, then F2 is said to dominate F1. • Dominance fault collapsing: If fault F2 dominates F1, then F2 is removed from the fault list. • When dominance fault collapsing is used, it is sufficient to consider only the input faults of Boolean gates. See the next example. • In a tree circuit (without fanouts) PI faults form a dominance collapsed fault set. • If two faults dominate each other then they are equivalent.

27. F2 s-a-1 Dominance Example All tests of F2 F1 s-a-1 001 110 010 000 101 100 011 Only test of F1 s-a-1 s-a-1 s-a-1 s-a-0 A dominance collapsed fault set

28. Checkpoints • Primary inputs and fanout branches of a combinational circuit are called checkpoints. • Checkpoint theorem: A test set that detects all single (multiple) stuck-at faults on all checkpoints of a combinational circuit, also detects all single (multiple) stuck-at faults in that circuit. Total fault sites = 16 Checkpoints ( ) = 10

29. Transistor (Switch) Faults • MOS transistor is considered an ideal switch and two types of faults are modeled: • Stuck-open -- a single transistor is permanently stuck in the open state. • Stuck-short -- a single transistor is permanently shorted irrespective of its gate voltage. • Detection of a stuck-open fault requires two vectors. • Detection of a stuck-short fault requires the measurement of quiescent current (IDDQ).

30. Stuck-Open Example Vector 1: test for A s-a-0 (Initialization vector) Vector 2 (test for A s-a-1) VDD pMOS FETs Two-vector s-op test can be constructed by ordering two s-at tests A 0 0 1 0 Stuck- open B C 0 1(Z) Good circuit states nMOS FETs Faulty circuit states

31. Stuck-Short Example Test vector for A s-a-0 VDD pMOS FETs IDDQ path in faulty circuit A Stuck- short 1 0 B Good circuit state C 0 (X) nMOS FETs Faulty circuit state

32. Functional vs. Structural ATPG

33. Carry Circuit

34. Functional vs. Structural(Continued) • Functional ATPG – generate complete set of tests for circuit input-output combinations • 129 inputs, 65 outputs: • 2129 = 680,564,733,841,876,926,926,749, 214,863,536,422,912 patterns • Using 1 GHz ATE, would take 2.15 x 1022 years • Structural test: • No redundant adder hardware, 64 bit slices • Each with 27 faults (using fault equivalence) • At most 64 x 27 = 1728 faults (tests) • Takes 0.000001728 s on 1 GHz ATE • Designer gives small set of functional tests – augment with structural tests to boost coverage to 98+ %

35. Exhaustive Algorithm • For n-input circuit, generate all 2n input patterns • Infeasible, unless circuit is partitioned into cones of logic, with 15 inputs • Perform exhaustive ATPG for each cone • Misses faults that require specific activation patterns for multiple cones to be tested

36. Random-Pattern Generation • Flow chart for method • Use to get tests for 60-80% of faults, then switch to D-algorithm or other ATPG for rest

37. History of Algorithm Speedups Algorithm D-ALG PODEM FAN TOPS SOCRATES Waicukauski et al. EST TRAN Recursive learning Tafertshofer et al. Est. speedup over D-ALG (normalized to D-ALG time) 1 7 23 292 1574 ATPG System 2189 ATPG System 8765 ATPG System 3005 ATPG System 485 25057 Year 1966 1981 1983 1987 1988 1990 1991 1993 1995 1997

38. Testability Measures • Definition • Controllability and observability • SCOAP measures • Combinational circuits • Sequential circuits • Summary

39. What are Testability Measures? • Approximate measures of: • Difficulty of setting internal circuit lines to 0 or 1 from primary inputs. • Difficulty of observing internal circuit lines at primary outputs. • Applications: • Analysis of difficulty of testing internal circuit parts – redesign or add special test hardware. • Guidance for algorithms computing test patterns – avoid using hard-to-control lines.

40. Testability Analysis • Determines testability measures • Involves Circuit Topological analysis, but no test vectors (static analysis) and no search algorithm. • Linear computational complexity • Otherwise, is pointless – might as well use automatic test-pattern generation and calculate: • Exact fault coverage • Exact test vectors

41. SCOAP Measures • SCOAP – Sandia Controllability and Observability Analysis Program • Combinational measures: • CC0 – Difficulty of setting circuit line to logic 0 • CC1 – Difficulty of setting circuit line to logic 1 • CO – Difficulty of observing a circuit line • Sequential measures – analogous: • SC0 • SC1 • SO • Ref.: L. H. Goldstein, “Controllability/Observability Analysis of Digital Circuits,” IEEE Trans. CAS, vol. CAS-26, no. 9. pp. 685 – 693, Sep. 1979.

42. Range of SCOAP Measures • Controllabilities – 1 (easiest) to infinity (hardest) • Observabilities – 0 (easiest) to infinity (hardest) • Combinational measures: • Roughly proportional to number of circuit lines that must be set to control or observe given line. • Sequential measures: • Roughly proportional to number of times flip-flops must be clocked to control or observe given line.

43. Combinational Controllability

44. Controllability Formulas(Continued)

45. Combinational Observability To observe a gate input: Observe output and make other input values non-controlling.

46. Observability Formulas(Continued) Fanout stem: Observe through branch with best observability.

47. Comb. Controllability Circled numbers give level number. (CC0, CC1)

48. Controllability Through Level 2

49. Final Combinational Controllability

50. Combinational Observability for Level 1 Number in square box is level from primary outputs (POs). (CC0, CC1) CO