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STR71x Training. MCD Application v1.2 – March 2004. CONTENTS. Objectives STR71x Device STR71x Family Block Diagram APB Buses Memory mapping and boot modes STR71x Library Library Structure Use Example STR71x Peripherals Features Software Library Programming Example. CONTENTS.

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Str71x training

STR71x Training

MCD Applicationv1.2 – March 2004


Contents
CONTENTS

  • Objectives

  • STR71x Device

    • STR71x Family

    • Block Diagram

    • APB Buses

    • Memory mapping and boot modes

  • STR71x Library

    • Library Structure

    • Use Example

  • STR71x Peripherals

    • Features

    • Software Library

    • Programming Example


Contents1
CONTENTS

  • Objectives

  • STR71x Device

    • STR71x Family

    • Block Diagram

    • APB Buses

    • Memory mapping and boot modes

  • STR71x Library

    • Library Structure

    • Use Example

  • STR71x Peripherals

    • Features

    • Software Library

    • Programming Example


Objectives
OBJECTIVES

  • Introduce the STR71x family

  • Improve your knowledge on STR71x peripherals

  • Introduce the STR71x Software Library

  • At the end of the training you will be able to :

    • List the main features of the STR71x peripherals and core

    • Configure the software library environment

    • Develop your applications using the STR71x Software Library


Contents2
CONTENTS

  • Objectives

  • STR71x Device

    • STR71x Family

    • Block Diagram

    • APB Buses

    • Memory mapping and boot modes

  • STR71x Library

    • Library Structure

    • Use Example

  • STR71x Peripherals

    • Features

    • Software Library

    • Programming Example


Str71x family

100,000 cycles endurance

No wait state

for embedded

RAM and FLASH

3.3V application supply and I/O interface

Embedded 1.8V voltage regulator for core supply

STR71x Family

ARM7TDMI

16/32 bit RISC CPU based host Micro

  • High Performance

  • Low Power Consumption


Str71x block diagram

ARM7TDMI

CPU

EMI

PRCCU

FLASH

JTAG

ARM7 native bus

RAM

APB1

APB2

I2C0

ADC

I2C1

EIC

BSPI0

TIM0

BSPI1

TIM1

UART0

TIM2

TIM3

UART1/SC

APB bus

APB bus

UART2

RTC

UART3

XTI

USB

WDG

CAN

GPIO0

HDLC

GPIO1

GPIO2

STR71x

STR71x Block Diagram

  • ARM7TDMI 16/32 bit RISC CPU

ARM7TDMI

CPU

EMI

PRCCU

  • Embedded Memory

    • FLASH : 256 kBytes + 16 kBytes

FLASH

RAM

  • RAM : 64 kBytes

  • EMI (TQFP144 only) : support of up to 4 banks of external SRAM, FLASH

APB1

APB2

  • Power Supply with low power modes :

    • 3.0V to 3.6V for I/Os

    • 3.0V to 3.6V for ADC

    • 1.8V for CPU and peripherals

  • 0-48 MHz frequency managed by PRCCU and PLL

  • 2 APB bridges :

    • APB1: communication peripherals

  • APB2: general purpose peripherals


Str71x apb buses

ARM7TDMI

CPU

EMI

PRCCU

FLASH

JTAG

ARM7 native bus

RAM

I2C0

APB1

APB2

I2C0

ADC12

I2C1

I2C1

EIC

BSPI0

TIM0

BSPI0

TIM0

BSPI1

TIM1

BSPI1

TIM1

UART0

TIM2

UART0

TIM2

TIM3

UART1/SC

TIM3

UART1/SC

APB bus

UART2

APB bus

UART2

RTC

UART3

UART3

XTI

USB

WDG

GPIO0

CAN

GPIO0

GPIO1

HDLC

GPIO1

GPIO2

GPIO2

STR71x

STR71x APB Buses

  • Connect native bus to devices

  • Clock Gating for peripherals

  • 4 kBytes for each mapped peripheral and dedicated registers

APB 1

APB 2

- 2 x I²C

ADC12

- 2 x BSPI

EIC

- 4 x UART

- 1 x USB

- 1 x CAN

- 1 x HDLC

RTC

- 1 x 12-bits Analog to Digital Converter

XTI

-Enhanced Interrupt Controller

USB

WDG

-4 x 16-bit Timers

- Real Time Clock

CAN

- External Interrupts

HDLC

- Watchdog Timer

- Up to 3 16-bit GPIOs


Memory mapping and boot modes

EIC

0xFFFF FFFF

EIC

APB2

0xFFFF FC00

RAM

FLASH

EXTMEM

APB2

APB1

0xE000 0000

APB1

RCCU

0xC000 0000

EXTMEM

RCCU

0xA000 0000

0x6000 0000

EXTMEM

FLASH

0x6000 0000

0x4000 0000

EN B1 B0

RAM

FLASH

0x2000 0000

0x4000 0000

Boot MEM

0x0000 0000

RAM

1

1

1

1

1

x

x

1

0

x

x

0

x

0

x

0x2000 0000

0x0000 0000

0x0000 0000

0x0000 0000

Boot MEM

0x0000 0000

Reserved

Memory Mapping and Boot Modes

  • Addressable memory space of 4 GBytes

  • RAM : 64 kBytes

  • FLASH : 256 kBytes + 16 kBytes

  • EXTMEM : 64 MBytes in 4 banks

Boot modes

A copy of RAM, EXTMEM or

FLASH will be aliased at 0x0

Depending on BOOTEN, BOOT0 and BOOT1 pins:

Memory remapping

Memory remapping can be done by software by programming the boot bits in the BOOTCR register


Contents3
CONTENTS

  • Objectives

  • STR71x Device

    • STR71x Family

    • Block Diagram

    • APB Buses

    • Memory mapping and boot modes

  • STR71x Library

    • Library Structure

    • Use Example

  • STR71x Peripherals

    • Features

    • Software Library

    • Programming Example


Library structure 1

Application Layer

User Application

Interface

Software Layer

Function 1

Function 2

Function m

Function 1

Function 2

Function k

Driver 1

Driver n

Hardware Layer

Peripheral 1

Peripheral i

Peripheral n

Library Structure (1)

  • Standard C language (only system parts are written in assembly)

  • Easy tool to access the peripheral functions

  • For each peripheral, a set of functions is defined to cover its features

  • Consistency in naming convention to make the code maintenance easier

  • Reduce the development time of new applications


Library structure 2

Application Layer

application.c

71x_conf.h

71x_it.c

71x_lib.h

71x_map.h

Software Layer

71x_type.h

gpio.h

71x_lib.c

71x_it.h

Hardware Layer

gpioX

Library Structure (2)

  • Global headers (includes all)

  • 71x_init.s: initializes modes and branches to main()

  • 71x_vect.s: exception vectors

  • retarget.c: retarget layer

  • scat.scf: specifies the memory mapping of the image to the linker

  • Peripheral driver source code

  • Interrupt functions’ headers

  • Peripheral functions’ headers

  • Interrupt functions source code

  • Peripheral registers’ addresses

  • Common types and constants

  • Configuration file

  • Peripherals pointers initialization

  • User application source code

gpio.c


Interrupt handling example
Interrupt Handling Example

71x_vect.s

71x_it.c

0x18

Branch to IRQHandler

subroutine

IRQHandler

“IRQ mode”

User program

“SYS mode”

Instruction

Subtract 4 from lr_irq

TIMIRQHandler

IRQ request

Instruction

Save r[0:12], spsr_irq

and lr_irq

Switch to SYS mode to

allow other IRQ interrupts

Execute the instruction

located in IVR

Instruction

Branch with link to

TIM_IRQHandler

TIMI_RQHandler

Clear the pending bit

TIM IRQ Handler

C code

Switch to IRQ mode

restore r[0:12], spsr_irq

and lr_irq

pc  lr_irq

cpsr  spsr_irq


Library use example 1
Library Use Example (1)

  • Common files must be copied to the working directory

  • To use the peripheral PPPx

    • Copy ppp.c and ppp.h files to the working directory

    • Edit the 71x_conf.h file and uncomment the following lines :

      • #define _PPP (mandatory)

      • #define _PPPx (optional, depending on the peripheral)

  • If you want to debug your application, you have to define the label DEBUG in the 71x_conf.h file :

    • #define DEBUG

  • Include this line in your application source code :

    • #include <71x_lib.h>


Library use example 2

71x_conf.h

#define DEBUG

#define _GPIO /* include gpio.h file */

#define _GPIO0 /* use GPIO0 peripheral */

71x_map.h

typedef volatile struct

{ u16 PC0; u16 EMPTY1;

u16 PC1; u16 EMPTY2;

u16 PC2; u16 EMPTY3;

u16 PD;} GPIO_TypeDef;

#define GPIO0_BASE (APB2_BASE + 0x3000)

#ifdef DEBUG

#ifdef _GPIO0

EXT GPIO_TypeDef *GPIO0;

#endif /* _GPIO0 */

#else /* NON DEBUG */

#define GPIO0 ((GPIO_TypeDef *)GPIO0_BASE)

#endif /* DEBUG */

Library Use Example (2)

  • 71x_lib.h

    #include "71x_type.h"

    #include "71x_conf.h"

    #include "71x_map.h"

    #ifdef _GPIO

    #include "gpio.h"

    #endif

To be modified by user

Do not modify this file

Define _GPIO in 71x_conf.h to include gpio.h in your project

Do not modify this file

  • main.c

    #include "71x_lib.h"

    int main

    {

    #ifdef DEBUG

    debug();

    #endif

    // main program

    }

User file

Include 71x_lib.h only

Pointers to peripherals structures are used in DEBUG mode

Initialize peripheral pointers when in DEBUG mode

Constants are used in NON DEBUG mode


Library programming warnings
Library Programming Warnings

!

  • Due to the ARM reduced instruction set, a read-modify-write access to memory locations or I/Os is interruptible (split into two basic instructions), so the user may have to put within critical sections the portions of code where a risk of data corruption exists :

    • Disable the interrupts that could occur

    • Start of the critical section

    • Do the access

    • End of the critical section

    • Re-enable the interrupts


Contents4
CONTENTS

  • Objectives

  • STR71x Device

    • STR71x Family

    • Block Diagram

    • APB Buses

    • Memory mapping and boot modes

  • STR71x Library

    • Library Structure

    • Use Example

  • STR71x Peripherals

    • Features

    • Software Library

    • Programming Example


Str71x peripherals power reset and clock control unit prccu
STR71x Peripherals Power, Reset and Clock Control Unit (PRCCU)


Power reset and clock control unit prccu

ARM7TDMI

CPU

EMI

PRCCU

FLASH

JTAG

ARM7 native bus

RAM

APB1

APB2

I2C0

ADC12

I2C1

EIC

BSPI0

TIM0

BSPI1

TIM1

UART0

TIM2

TIM3

UART1/SC

APB bus

APB bus

UART2

RTC

UART3

XTI

USB

WDG

CAN

GPIO0

HDLC

GPIO1

GPIO2

STR71x

Power, Reset and Clock Control Unit (PRCCU)

PRCCU


Power reset and clock control unit
Power, Reset and Clock Control Unit

  • Separate Power Block with enhanced power saving features

  • Reset Management block with Hardware and software reset sources

  • Clock Control Unit with a wide range of clock frequency and sources


Reset unit
Reset Unit

  • Hardware and Software Reset

  • Reset pad (Input only) with an analog filter to improve EMC susceptibility

  • Internal Watchdog Reset

  • Low Voltage Detector Reset


Clock control unit

OSC 32kHz

RTC

RTCXI

PRCCU

RTCXO

CK_AF

MCLK

MCLK

DIV2/4/8

to Core and Memories

1/16

RCLK

PCLK1

DIV2/4/8

to Fast Peripherals on APB1

CLK3

CLK2

PCLK2

1/2

CK

DIV2/4/8

to Slow Peripherals on APB2

PLL1

PLL1

CKOUT

HDLC

PLL2

PLL2

HCLK

48MHz

USB

USBCLK

Clock Control Unit

  • Two separate PLLs :

    • PLL Multiplier of 12,16, 20 and 28

    • PLL Divider from 1 to 7

  • 4 clock sources

  • Main clock system up to 48 MHz

  • Separate clock activation for each peripheral



Power block

3.3V

IO RING

Main

Regulator

Low Power

Regulator

Main

Regulator

Low Power

Regulator

Core

1.8V

1.8V

1.8V Backup

IO

RTC

Low Power

Logic

Power Block

  • Single External 3.3 V power supply and I/O capability

  • 4 Power Saving Modes :

    • Slow

    • Wait For Interrupt

    • Stop

    • Standby

  • 2 Embedded regulators with external 1.8V capacitors

    • Main Voltage Regulator

    • Low Power Voltage Regulatior

3.3V

1.8V Backup

IO

RTC

Low Power

Logic


Low power modes 1 3
Low Power Modes (1/3)

RUN

Full power mode

WFI Mode

You reduce power consumption by stopping the core. Peripherals are kept running and the register contents are preserved

Slow Mode

You reduce power consumption by slowing down the main clock

Stop Mode

You stop all clocks without resetting the device, hence preserving the MCU status. The internal power is maintained

Standby Mode

In Standby mode, the main Voltage Regulator is switched off internally, and the kernel of the device is powered off. Exit with RTC, WAKEUP IT, Reset


Low power modes 1 31
Low Power Modes (1/3)

  • Wait For Interrupt Mode (WFI)

    • CPU forced to the wait mode

    • Software configurable Internal slow clock or external RTC clock

    • Automatic context saving

    • Resume events : External Wake-up pin, RTC alarm

    • Software configurable Low Power Mode activation

  • SLOW Mode

    • Software configurable slow clock selection

    • 3 different slow clock sources : CLK2, CLK2/16, CK_AF

  • Low Power WFI Mode

    • Combination of WFI and SLOW Modes


Low power modes 3 3
Low Power Modes (3/3)

  • STOP Mode

    • All system clocks are stopped

    • Power supply is maintained for the whole chip

    • Automatic context saving

    • Resume events : external Wake-up pin, RTC alarm

    • Configurable Exit STOP mode interrupt

  • STAND BY Mode

    • All system clocks are stopped

    • All I/O pads forced to High impedance

    • V18 Power supply is switched off

    • Separate Power supply for backup block

    • System status monitored by the nSTDBY pad



Prccu programming example
PRCCU Programming Example

This example configures the Clock Control Unit to generate 40 MHz for the main system clock and 20 MHz for APB1 and APB2 peripherals with CK = 16 MHz.

Configuration Steps

Programming Steps

{

  • Select the Clock2 as active clock

RCCU_RCLKSourceConfig(RCCU_CLOCK2);

  • Configure the PLL1 parameters

RCCU_PLL1Config(RCCU_Mul_20, RCCU_Div_4);

  • Select the PLL1 output clock as active clock

RCCU_RCLKSourceConfig(RCCU_PLL1_Output);

  • Main system Clock is equal to PLL1 output clock

RCCU_MCLKConfig(RCCU_DEFAULT);

  • APB2 Clock is equal to PLL1 output clock divided by 2

RCCU_PCLKConfig(RCCU_RCLK_2);

RCCU_FCLKConfig(RCCU_RCLK_2);

}

  • APB1 Clock is equal to PLL1 output clock divided by 2


Str71x peripherals external memory interface emi
STR71x PeripheralsExternal Memory Interface(EMI)


External memory interface emi

ARM7TDMI

CPU

EMI

PRCCU

FLASH

JTAG

ARM7 native bus

RAM

APB1

APB2

I2C0

ADC12

I2C1

EIC

BSPI0

TIM0

BSPI1

TIM1

UART0

TIM2

TIM3

UART1/SC

APB bus

APB bus

UART2

RTC

UART3

XTI

USB

WDG

CAN

GPIO0

HDLC

GPIO1

GPIO2

STR71x

External Memory Interface (EMI)

EMI


Emi features
EMI Features

  • 4 external regions/chip select (memory banks)

  • Each bank is fully configurable :

    • Can address up to 16 MBytes external memory space

    • Up to 15 wait states in read/write cycles

    • Programmable data bus size (16 or 8 bits)

    • Independent enabling/disabling


Emi access cycles

MCLK

C_Length[3:0]

0x3

B_Size[1:0]

0x1

RDn

Access Length (3 wait states)

CSn2

WEn0

WaitCycle

WaitCycle

WaitCycle

WEn1

A[1:0]

0x0

A[23:2]

Address[23:2]

D[15:0](output)

Data[15:0]

EMI Access Cycles

Timing diagram of a 16-bit write cycle on a 16-bit external memory, with 3 wait states.


Emi programming example

BCR0

BCR1

BCR1

BCR0

15

15

15

15

14

14

14

14

13

13

13

13

12

12

12

12

11

11

11

11

10

10

10

10

9

9

9

9

8

8

8

8

7

7

7

7

6

6

6

6

5

5

5

5

4

4

4

4

3

3

3

3

2

2

2

2

1

1

1

1

0

0

0

0

0

BE

BE

1

-

-

-

-

C_LENGTH

x

C_LENGTH

5

0

x

B_SIZE

B_SIZE

EMI Programming Example

This example shows how to access the EMI.

Configuration Steps

Programming Steps

{

GPIO_Config(GPIO2, 0x000F, GPIO_AF_PP);

  • Configure the I/Os as Alternate Function

  • Disable Bank 0

EMI_Config(0, EMI_DISABLE);

  • Enable Bank 1 with 5 wait state and 8-bit data bus

EMI_Config(1, EMI_ENABLE | EMI_WAITSTATE(5) | EMI_SIZE_8);

  • Write 0x12345678 data to Bank 1

*(u32*)(0x62000000) = 0x12345678;

data = *(u32*)(0x62000000);

}

  • Read data from Bank 1

!

Don’t forget to configure the GPIO2 port pins as Alternate Function Push-Pull


Str71x peripherals on chip flash memory
STR71x PeripheralsOn-chip Flash Memory


On chip flash memory

ARM7TDMI

CPU

EMI

PRCCU

FLASH

JTAG

ARM7 native bus

RAM

APB1

APB2

I2C0

ADC12

I2C1

EIC

BSPI0

TIM0

BSPI1

TIM1

UART0

TIM2

TIM3

UART1/SC

APB bus

APB bus

UART2

RTC

UART3

XTI

USB

WDG

CAN

GPIO0

HDLC

GPIO1

GPIO2

STR71x

On-chip Flash Memory

FLASH


Flash features
Flash Features

  • 2 separate banks :

    • Bank 0 : containing 256 kBytes of memory divided in 8 sectors

    • Bank 1 : containing 16 kBytes of memory divided in 2 sectors

  • Internal management of write (program or erase) sequence.

  • Erase operation on sectors (each sector can be erased independently).

  • Program operation on single word (32-bits) or double word (64-bits).

  • Suspend of on-going write operation

  • You can read from one bank while writing to the other.

  • 2 operating modes :

    • Random: read operation are performed with zero wait states up to 33 MHz

    • Burst: sequential accesses are performed with zero wait states up to 48 MHz

  • 2 protection strategies :

    • Write protection: A sector can be write Protected

    • Debug protection: debug features and JTAG pins are disabled


Flash programming example
Flash Programming Example

The following example writes data to the sector 0 and 1 then erases all the flash module.

Configuration Steps

Programming Steps

{

FLASH_Init();

  • Initialize the Flash registers

  • Write 0x12345678 data to the sector 0, bank 0 of the Flash module

FLASH_WordWrite(0x00000000, 0x12345678);

  • Write 0x87654321 data to the sector 0, bank 1 of the Flash module

FLASH_WordWrite(0x000C0000, 0x87654321);

  • Erase all the Flash Module

FLASH_ModuleErase();

}


Str71x peripherals advanced peripheral bus apb
STR71x PeripheralsAdvanced Peripheral Bus(APB)


Apb overview

ARM7TDMI

CPU

EMI

PRCCU

FLASH

JTAG

ARM7 native bus

RAM

APB1

APB2

APB1

APB2

I2C0

ADC12

I2C1

EIC

BSPI0

TIM0

BSPI1

TIM1

UART0

TIM2

TIM3

UART1/SC

APB bus

APB bus

APB bus

APB bus

UART2

RTC

UART3

XTI

USB

WDG

CAN

GPIO0

HDLC

GPIO1

GPIO2

STR71x

APB Overview

  • The APB bridges allows the connection between the ARM7 native bus and peripherals mapped on the APB buses.

  • 2 separate bridges :

    • APB1 : For fast peripherals such as I²C, UART, USB, CAN, SPI, HDLC.

  • APB2 : For slow peripherals such as EIC, XTI, GPIOs, ADC12, Timer, RTC, Watchdog.


Apb bridges features
APB Bridges Features

  • Peripheral Clock: The APB bridges controls the clock gating for all the peripherals. Each peripheral’s clock signal can be activated or disabled through the CKDIS register.

  • Peripheral Reset: The APB bridges control the Reset for all the peripherals. Each peripheral can be configured through the SWRES register to be reset or not.


Apb programming example

1

1

1

1

0

APB Programming Example

The following example configures the clock and reset for the UART0 and UART1 peripherals (on APB1).

Configuration Steps

Programming Steps

{

APB_ClockConfig(APB1,

UART0_Periph | UART1_Periph,

DISABLE);

  • Disable the Clock of the UART0 and UART1 peripherals

APB_ClockConfig(APB1,

UART2_Periph,

ENABLE);

  • Enable the Clock for the UART2

APB_SwResetConfig(APB1,

UART0_Periph | UART1_Periph,

ENABLE);

  • The UART0 and UART1 are kept under Reset

APB_SwResetConfig(APB1,

UART2_Periph,

DISABLE);

}

  • Disable reset status for the UART2

CKDIS

CKDIS

SWRES

X

X


Str71x peripherals 12 bit analog to digital converter adc12
STR71x Peripherals12-bit Analog-to-Digital Converter(ADC12)


Analog to digital converter adc

ARM7TDMI

CPU

EMI

PRCCU

FLASH

JTAG

ARM7 native bus

RAM

APB1

APB2

I2C0

ADC12

I2C1

EIC

BSPI0

TIM0

BSPI1

TIM1

UART0

TIM2

TIM3

UART1/SC

APB bus

APB bus

UART2

RTC

UART3

XTI

USB

WDG

CAN

GPIO0

HDLC

GPIO1

GPIO2

STR71x

Analog-to-Digital Converter (ADC)

ADC12


Adc12 features

Sleep_mod

VCM

Vref

Data Register 0

Data Register 0

P0.0

P0.0

∑ - ∆

Modulator

∑ - ∆

Modulator

Data Register 1

Data Register 1

Sinc3

Filter

Sinc3

Filter

P0.1

P0.1

Mux

Output

Data Register 2

Data Register 2

P0.2

P0.2

P0.3

P0.3

Data Register 3

Data Register 3

Clock Prescaler Register

Control/Status Register

IRQ

IRQ

ADC12 Features

  • 4 Data registers to store conversion result for each channel

  • 12-bit resolution

  • Input voltage range : 0 - 2.5V

  • 4 Flags showing the availability of conversion result

  • Sigma-Delta Architecture

  • 4 Analog input channels

  • Clock configuration:

    PRESCALER = APB2_FREQ / (SAMPLE_FREQ * 512 * 4)

  • 2 Conversion modes :

    • Round-robin (up to 500 Hz / 2 ms)

  • End of conversion interrupt

  • Single channel (up to 2 kHz / 500 µs)

Clock Prescaler Register

Control/Status Register


Adc12 operation modes

Select Input Channel

Select Input Channel

Reset Modulator

Reset Modulator

Clear Digital Filter

Clear Digital Filter

Acquire Analog Data

Acquire Analog Data

Sinc3 Filter

Sinc3 Filter

Output 16-bit Sample

Output 16-bit Sample

Reset Converter

Shift Input Channel

ADC12 Operation Modes

  • Single Channel Operation

  • Normal Operation (Round Robin)

512 oversampling clock cycles

Taken out every2048 clock cycles


Adc12 programming example

CSR

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

BOOTCR

x

x

x

x

x

x

1

x

x

x

x

x

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

x

x

x

x

x

0

x

x

x

x

BOOTCR

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

CPRR

-

PKG64

X

HDLC

CAN

ADCEN

LPOW

USB

SPI0

BOOT

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

x

PRESC[6:0]

BOOTCR

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

x

x

x

x

x

1

x

x

x

x

CSR

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

-

-

OR

-

IE[3:0]

-

AXT

A[1:0]

DA3

DA2

DA1

DA0

CPRR

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

x

0

0

1

0

0

0

0

CSR

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

x

x

x

x

x

x

x

x

1

x

x

x

DATA3

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

DATA[11:0]

-

CSR

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

X

x

x

x

x

x

x

1

1

x

x

x

x

ADC12 Programming Example

This example shows how to use the analog-to-digital converter in the single channel mode.

Configuration Steps

Programming Steps

{

ADC12_Init();

  • Initialize the converter

  • Configure the I/O port to analog input

GPIO_Config(GPIO1, 0x0001, GPIO_HI_AIN_TRI);

  • Enable the converter

ADC12_ConversionStart();

  • Configure the prescaler

ADC12_PrescalerConfig(500);

  • Configure mode of conversion

ADC12_ModeConfig(ADC12_SINGLE);

  • Select channel to be converted

ADC12_ChannelSelect(ADC12_CHANNEL0):

while (!ADC12_FlagStatus(ADC12_DA0));

  • Wait until the Data Available flag is set

ADC12_ConversionValue(ADC12_CHANNEL0);

  • Get the conversion result

ADC12_ConversionStop();

}

  • Disable the converter

!

Don’t forget to configure the GPIO1 port pins as High Impedance Analog Input


Str71x peripherals enhanced interrupt controller eic
STR71x PeripheralsEnhanced Interrupt Controller(EIC)


Enhanced interrupt controller eic

ARM7TDMI

CPU

EMI

PRCCU

FLASH

JTAG

ARM7 native bus

RAM

APB1

APB2

I2C0

ADC12

I2C1

EIC

BSPI0

TIM0

BSPI1

TIM1

UART0

TIM2

TIM3

UART1/SC

APB bus

APB bus

UART2

RTC

UART3

XTI

USB

WDG

CAN

GPIO0

HDLC

GPIO1

GPIO2

STR71x

Enhanced Interrupt Controller(EIC)

EIC


Eic features

SIR

Interrupt

Vector

Table

(32 entry)

Interrupt

Vector

Table

(32 entry)

Interrupt from line IRQn

IRQn vector

IVR

IVR[31:16]

IVR[31:16]

SIR[31:16]

SIR[31:16]

Highest priority interrupt

IER

IPR

CIPR

IRQ0

IE0

IE0

IP0

IP0

Current

Interrupt

Priority

Current

Interrupt

Priority

Priority

Stack

(16 entry)

Priority

Stack

(16 entry)

Stack Control (PUSH/POP)

IRQ1

IE1

IE1

IP1

IP1

IRQ

Control logic

IRQ

Control logic

IRQ Request

IRQ to ARM core

IRQ31

IE31

IE31

IP31

IP31

ICR

FIQ_EN

FIQ_EN

IRQ_EN

IRQ_EN

FIR

FIP

FIQ to ARM core

FIQ Request

FIQ

Control logic

FIQ

Control logic

FIQ0

FIE0

FIE0

FIP0

FIP0

FIQ1

FIE1

FIE1

FIP1

FIP1

EIC Features

  • Hardware handling of multiple interrupt channels, interrupt priority and automatic vectorization.

  • 32 maskable interrupt channels, mapped on ARM’s interrupt request pin IRQ.

  • 16 programmable priority levels for each interrupt channels mapped on IRQ.

  • Hardware support for interrupt nesting (15 levels).

  • 2 maskable interrupt channels, mapped on ARM’s fast interrupt request pin FIQ, with neither priority nor vectorization.


Eic priority levels and arbitration
EIC Priority Levels and Arbitration

  • The channel priority level is defined in the range 0-15

    • level 15 is the highest priority

    • level 0 is the lowest

  • An interrupt requesting channel, to be the winner, must :

    • be enabled in the IER (Interrupt Enable Register)

    • have the highest priority level related to the current interrupt requests, and higher than the current one

  • All the interrupt sources that have a priority level less or equal to main program level will never generate an IRQ request, even if properly enabled


Programming tips eic configuration
Programming TipsEIC Configuration

  • To detect an IRQ interrupt

    • Set in field SIPLn of SIRn the channel priority level (it must be not 0 to have an IRQ to be generated)

    • Write in SIVn (SIRn[31:16])the memory address offset (or the jump offset) where the Interrupt Service Routine, related to interrupt starts

    • Insert the base jump address (or the jump opcode) in the IVR[31:16]

    • Set IERn bits to enable the desired channels

    • Set the IRQ_EN bit of ICR to 1

  • To detect an FIQ interrupt

    • Set bit 0 or 1 of FIE in FIR register to 1

    • Set the FIQ_EN bit of ICR to 1


Example of irq interrupt handling

IRQ1

0

1

Example of IRQ Interrupt Handling

The ARM7TDMI IRQ line is asserted low until the IVR is read.

When the IVR is read, the EIC saves the previous interrupt priority and the channel ID in the stack.

Before exiting the interrupt service,

The IPn is set

If the IRQ request is accepted by the EIC

When the IRQ line is set

and update the CICR by the new channel ID

Finally the EIC restore the previous interrupt priority, IVR[15:0] and the channel ID.

the sofware has to clear the related interrupt pending bit

The EIC updates the current interrupt priority register with the new priority

IVR [15:0] is updated by SIRn[31:16] content

SIR0

0

0xF820

IER

IPR

4

4

4

0xF824

SIR1

4

0xF824

0xF824

0xF824

0

0

0xE59FF824

0xE59FF820

0xE59FF824

SIR2

...

SIR31

1

1

0

0

0xF820

F820

0xF824

0xE59F

IVR

IRQ Control Logic

Priority Stack (16 entry)

0

4

0

CIPR

0

0

0

IRQ to ARM7TDMI

ICR


Eic programming example

IER

IER

ICR

ICR

ICR

ICR

31

31

31

31

31

31

4

4

3

3

2

2

1

1

1

1

1

1

0

0

0

0

0

0

FIR

FIR

0

0

//

//

0

0

0

0

1

0

0

0

FIQ_EN

FIQ_EN

1

FIQ_EN

0

0

IRQ_EN

1

1

1

SIR2

SIR2

31

31

4

4

3

3

2

2

1

1

0

0

31

31

16

16

3

3

0

0

-

-

FIP1

FIP1

FIP0

FIP0

FIE1

0

FIE0

1

Offset

SIV2[31:16]

-

-

SIPL2[3:0]

4

EIC Programming Example

This example shows how to use the EIC to enable the channel 2 IRQ interrupts and the FIQ interrupts.

Configuration Steps

Programming Steps

{

EIC_IRQChannelPriorityConfig(RCCU_IRQChannel, 4);

  • Set the IRQ channel 2 priority to 4

  • Enable the IRQ channel 2 interrupts

EIC_IRQChannelConfig(RCCU_IRQChannel, ENABLE);

  • Enable IRQ interrupts

EIC_IRQConfig(ENABLE);

  • Enable FIQ Channel 0 interrupts

EIC_FIQChannelConfig(T0TIMI_FIQChannel, ENABLE);

  • Enable FIQ interrupts

EIC_FIQConfig(ENABLE);

}



Timer

ARM7TDMI

CPU

EMI

PRCCU

FLASH

JTAG

ARM7 native bus

RAM

APB1

APB2

I2C0

ADC12

I2C1

EIC

BSPI0

TIM0

TIM0

BSPI1

TIM1

TIM1

UART0

TIM2

TIM2

TIM3

UART1/SC

TIM3

APB bus

APB bus

UART2

RTC

UART3

XTI

USB

WDG

CAN

GPIO0

HDLC

GPIO1

GPIO2

STR71x

Timer


Timer features

Timer Peripheral Interface

PCLK

16

16

16

16

16

16-bit

Counter

EXEDG

16-bit

Counter

16-bit

Counter

16-bit

Counter

16-bit

Counter

16-bit

Counter

Output

Compare

reg. A

Output

Compare

reg. A

Output

Compare

reg. A

Output

Compare

reg. B

Output

Compare

reg. B

Input

Capture

reg. A

Input

Capture

reg. A

Input

Capture

reg. B

Input

Capture

reg. B

Output

Compare

reg. A

Output

Compare

reg. B

Input

Capture

reg. A

Input

Capture

reg. B

1/CC

Counter

Alternate

register

EXTCLK

Output Compare

Circuit

Output Compare

Circuit

Output Compare

Circuit

Output Compare

Circuit

CC0..6

ECKEN

Overflow

Detection

Circuit

Edge Detect

Circuit B

Edge Detect

Circuit B

ICAPB

Edge Detect

Circuit B

Edge Detect

Circuit A

Edge Detect

Circuit A

Edge Detect

Circuit A

ICAPA

OCMPA

Latch A

Latch A

Latch A

Latch A

OCMPB

Latch B

Latch B

Status Register

Status Register

Status Register

Status Register

Control Registers 1 & 2

Control Registers 1 & 2

Control Registers 1 & 2

Control Registers 1 & 2

Control Registers 1 & 2

Control Registers 1 & 2

Control Registers 1 & 2

Timer Features

  • Software configurable clock and active edge selection

16-bit

Counter

1/CC

  • Free running, 16-bit up counter

  • Configurable prescaler (1 to 256)

  • 5 Operation modes :

  • Input capture

  • Output compare

  • One pulse

  • PWM output

  • PWM input


Timer input capture mode

Timer Counter Register

Edge Detector

Input Capture Register

ICAP1A

Software Maskable Interrupt Request

Timer Input Capture Mode

  • Captures the counter value upon input signal edge detection

  • Allows an external pulse length measurement


Timer output compare mode

Timer Counter Register

Software Maskable Interrupt

RequestPulse generation

Match?

Output Compare Register

Timer Output Compare Mode

  • Event generation (Interrupt request/bit toggling) whenever the compare register matches the counter

  • Indicates a period of time has elapsed

  • Controls an output waveform


Timer one pulse mode

Generation of a pulse synchronized with an external event

Counter

FFFC

FFFE

2ED0

2ED1

2ED3

FFFC

FFFD

2ED2

ICAPA

OLVLA

OLVLB

OLVLB

OCMPA

Compare A

Timer One Pulse Mode

2ED0

FFFC

IEDGA = 1

OCAR = 0x2ED0

OLVLA = 0

OLVLB = 1

  • On Input Capture event

  • The counter is reset to 0xFFFC

  • The timer output pin is toggled to the OLVLB level

  • On Output compare event

  • The timer output pin is toggled to the OLVLA level

  • The timer waits for the next Input Capture event


Timer pwm output mode

Automatic generation of a Pulse Width Modulated signal

Counter

FFFC

FFFE

2ED0

2ED1

FFFC

34E2

FFFD

34E2

OLVLA

OLVLB

OLVLB

OCMPA

Compare B

Compare A

Compare B

Timer PWM Output Mode

  • Similar to the One Pulse Mode where the Input Capture event is replaced by the second Output Compare event

OCAR = 0x2ED0

2ED0

34E2

OCBR = 0x34E2

OLVLA = 0

OLVLB = 1

  • The Output Compare A Register contains the length of the pulse

  • The OLVLB bit contains the level during the pulse

  • The Output Compare B Register contains the period of the pulse

  • The OLVLB bit contains the level after the pulse


Timer pwm input mode

External pulse and period measurement of an external wave

Counter

0000

0002

2ED0

2ED1

0000

34E2

0001

34E2

ICAPA

Capture A

Capture B

Capture A

Period = ICAPA

Pulse Length = ICAPB

Timer PWM Input Mode

  • Programmable first edge detection

  • Interrupt Generation

ICAR = 0x2ED0

ICBR = 0x34E2

IEDGA = 1

IEDGB = 0

  • The First edge is configured through the IEDGA bit

  • The Second edge is configured through the IEDGB bit

  • The signal Full period is stored in the ICAPA

  • The Pulse length is stored in the ICAPB


Timer programming example
Timer Programming Example

This example configures the Timer 3 to generate an interrupt each time a valid falling edge is detected on the input capture A channel.

Configuration Steps

Programming Steps

{

TIM_Init(TIM3);

  • Initialize the Timer 3 peripheral

  • Configure the ICAPA as input pin

GPIO_Config(GPIO1, TIM3_ICAP_A, GPIO_IN_TRI_TTL);

  • Configure the Input capture mode

TIM_ICAPModeConfig(TIM3, TIM_CHANNEL_A, TIM_FALLING);

  • Enable the Input Capture Interrupt

TIM_ITConfig(TIM3, TIM_ICA_IT, ENABLE);

  • Enable the Timer IRQ channel

EIC_IRQChannelConfig(T3TIMI_IRQChannel, ENABLE);

EIC_IRQChannelPriorityConfig(T3TIMI_IRQChannel, 1);

EIC_IRQConfig(ENABLE);

  • Start the Timer Counter

TIM_CounterConfig(TIM3, TIM_START);

}

!

Don’t forget to configure the GPIO1 port pins as Input Tristate TTL


Str71x peripherals real time clock rtc
STR71x PeripheralsReal Time Clock(RTC)


Real time clock rtc

ARM7TDMI

CPU

EMI

PRCCU

FLASH

JTAG

ARM7 native bus

RAM

APB1

APB2

I2C0

ADC12

I2C1

EIC

BSPI0

TIM0

BSPI1

TIM1

UART0

TIM2

TIM3

UART1/SC

APB bus

APB bus

UART2

RTC

UART3

XTI

USB

WDG

CAN

GPIO0

HDLC

GPIO1

GPIO2

STR71x

Real Time Clock (RTC)

RTC


Rtc features

RTCL

RTCL

RTCL

RTCA

RTCA

Reload

=

RTCD

RTCD

32 kHz

32 kHz

RTCCNT

RTCCNT

RTCCR

GloInt

OwInt

Alarm

SecInt

GloInt

OwInt

Alarm

SecInt

RTC Features

  • Software configurable prescaler

  • 32-bit software programmable counter

  • External 32 kHz clock input

  • Interrupt capability : 3 maskable interrupts

    • Second interrupt

RTCCNT

  • Alarm interrupt

  • Overflow interrupt

  • Global Interrupt

  • Register protection against unwanted write operations


Rtc configuration mode
RTC Configuration Mode

To write to the RTCL, RTCCNT and RTCA registers the peripheral should enter in the configuration mode.

Configuration Mode Steps

  • Waiting until the last operation is finished (RTOFF = 1)

  • Set the CNF bit

  • Write one or more RTC registers

  • Reset the CNF bit

RTC Control Register Low (RTCCRL)

RTOFF

CNF


Rtc programming example
RTC Programming Example

The following example sets the RTC alarm value, when the RTC counter value reach the RTC alarm value an Alarm interrupt will be generated by the RTC.

Configuration Steps

Programming Steps

{

RTC_PrescalerConfig(0x8000);

  • Configure the RTC prescaler to 0x8000

  • Set the RTC Time to 8:30:00

RTC_SetTime(8, 30, 00);

  • Set the RTC alarm Time to 8:31:30

RTC_SetAlarmTime(8, 31, 30);

  • Enable the RTC alarm Interrupt

RTC_ITConfig(RTC_AIT, ENABLE);

EIC_IRQChannelConfig(RTC_IRQChannel, ENABLE);

  • Enable the RTC IRQ channel

EIC_IRQChannelPriorityConfig(RTC_IRQChannel, 4);

EIC_IRQConfig(ENABLE);

RTC_GITConfig(ENABLE);

}

  • Enable the RTC Global Interrupt


Str71x peripherals external interrupts xti
STR71x PeripheralsExternal Interrupts(XTI)


External interrupts xti

ARM7TDMI

CPU

EMI

PRCCU

FLASH

JTAG

ARM7 native bus

RAM

APB1

APB2

I2C0

ADC12

I2C1

EIC

BSPI0

TIM0

BSPI1

TIM1

UART0

TIM2

TIM3

UART1/SC

APB bus

APB bus

UART2

RTC

UART3

XTI

USB

WDG

CAN

GPIO0

HDLC

GPIO1

GPIO2

STR71x

External Interrupts (XTI)

XTI


Xti features

External Interrupts Lines

[7..2]

[15..8]

[7..2]

[15..8]

Triggering Level Registers

TRL

TRH

TRL

TRH

Software

Interrupt

Register

Pending Request Registers

PRL

PRH

Mask Registers

SR

MRL

MRH

SR

MRL

MRH

SW setting

Control Register

ID1S

STOP

to PRCCU

Stop Mode Control

to PRCCU

Stop Mode Control

WKUP_INT

to EIC

IRQ 5

to EIC

IRQ 5

XTI Features

  • Supports up to 16 interrupts sources individually maskable

    • Software IRQ interrupt (interrupt source 0)

    • USB wake-up event: generated while exiting from suspend mode (interrupt source 1)

    • 14 external interrupt lines (interrupt sources [15..2])

  • Programmable trigger edge polarity

    • Falling edge

    • Rising edge

  • External interrupts can be used to wake-up the system from STOP mode

  • Programmable selection of Wake-up / Wake-up with interrupt

  • Connected to IRQ 5 channel of the Enhanced Interrupt Controller module


Xti configuration interrupt mode
XTI ConfigurationInterrupt Mode

  • To configure an external interrupt, proceed as follows :

    • Configure the mask bits of the external interrupts (MRL, MRH)

    • Configure the triggering edge registers of the external interrupts (TRL, TRH)

    • Set the ID1S bit in the CTRL register to enable the external interrupt

    • Configure the corresponding I/O pins to Weak Push-Pull Output mode

    • Don’t forget to enable the XTI interrupts in the EIC and to set the XTI channel priority level


Xti configuration wake up mode
XTI ConfigurationWake-Up Mode

  • To configure an external interrupt line as a wake-up source, proceed as follows :

    • Configure the mask bits of the external interrupts (MRL, MRH)

    • Configure the triggering edge registers of the external interrupts (TRL,TRH)

    • Set the WKUP-INT bit in the CTRL register to select Wake-up Mode

    • Configure the corresponding I/O pins to Weak Push-Pull Output mode

    • To enter STOP mode, write the sequence 1,0,1 to the STOP bit of the CTRL register


Xti programming example

TRL

CTRL

MRL

TRH

MRH

7

7

7

7

7

6

6

6

6

6

5

5

5

5

5

4

4

4

4

4

3

3

3

3

3

2

2

2

2

2

1

1

1

1

1

0

0

0

0

0

x

1

x

1

-

x

x

x

x

x

x

x

x

x

x

x

x

x

x

x

x

0

x

1

x

0

x

1

x

x

x

0

x

x

x

x

XTI Programming Example

This example shows how to use the XTI to enable the channel 2 IRQ interrupts and the FIQ interrupts.

Configuration Steps

Programming Steps

{

XTI_LineModeConfig(XTI_Line2, XTI_FallingEdge);

  • Set the Line 2 edge to falling edge

  • Enable the External interrupts on line 2

XTI_LineConfig(XTI_Line2, ENABLE);

  • Set the Line 15 edge to rising edge

XTI_LineModeConfig(XTI_Line15, XTI_RisingEdge);

  • Enable external interrupts on line 15

XTI_LineConfig(XTI_Line15, ENABLE);

  • Enable Interrupt mode

XTI_ModeConfig(XTI_Interrupt, ENABLE);

}


Str71x peripherals watchdog timer wdg
STR71x PeripheralsWatchdog Timer(WDG)


Watchdog timer wdg

ARM7TDMI

CPU

EMI

PRCCU

FLASH

JTAG

ARM7 native bus

RAM

APB1

APB2

I2C0

ADC12

I2C1

EIC

BSPI0

TIM0

BSPI1

TIM1

UART0

TIM2

TIM3

UART1/SC

APB bus

APB bus

UART2

RTC

UART3

XTI

USB

WDG

CAN

GPIO0

HDLC

GPIO1

GPIO2

STR71x

Watchdog Timer(WDG)

WDG


Wdg features

WDG_VR

WDG_PR

8-bit

Prescaler

16-bit

Counter

SYS_RES

PCLK2

EC_INT

EC_INT

SC

WE

WDG_CR bits

WDG Features

  • 2 operating modes :

    • Watchdog

    • Timer

  • 8-bit clock prescaler

  • 16-bit down counter

8-bit

Prescaler

16-bit

Counter

  • Safe reload sequence

  • Free-running timer mode

  • End-of-count interrupt generation


Wdg programming example 1 2
WDG Programming Example (1/2)

This example shows how to implement a watchdog interrupt.

Programming Steps

Configuration Steps

{

WDG_ECITConfig(DISABLE);

  • Disable the end-of-count interrupt

  • Stop the timer counter

WDG_CntOnOffConfig(DISABLE);

  • Set the timer period to 12345 µs

WDG_PeriodValueConfig(12345);

  • Set the priority of the watchdog IRQ

EIC_IRQChannelPriorityConfig(WDG_IRQChannel, 1);

  • Enable the watchdog IRQ

EIC_IRQChannelConfig(WDG_IRQChannel, ENABLE);

  • Enable globally the interrupts

EIC_IRQConfig(ENABLE);

  • Enable the end-of-count interrupt

WDG_ECITConfig(ENABLE);

  • Start the timer to count down

WDG_CntOnOffConfig(ENABLE);

}

Each time the timer period is elapsed, the WDG_IRQHandler() function is called.


Wdg programming example 2 2
WDG Programming Example (2/2)

This example shows how to handle the watchdog mode with auto-reset.

Configuration Steps

Programming Steps

{

WDG_ECITConfig(DISABLE);

  • Disable the end-of-count interrupt

  • Stop the timer counter

WDG_CntOnOffConfig(DISABLE);

  • Set the prescaler register to 0xFF

WDG_PrescalerConfig(0xFF);

  • Set the preload register to 1613

WDG_CntReloadUpdate(1613);

  • Enable the watchdog mode (cannot be disabled)

WDG_Enable();

while (condition)

{

  • Refresh periodically the timer counter to avoid a system reset

WDG_CntRefresh();

}

}

As soon as the timer counter is no more refreshed and its value reaches 0, the system is reset.


Str71x peripherals general purpose input output gpio
STR71x PeripheralsGeneral Purpose Input/Output(GPIO)


General purpose input output gpio

ARM7TDMI

CPU

EMI

PRCCU

FLASH

JTAG

ARM7 native bus

RAM

APB1

APB2

I2C0

ADC12

I2C1

EIC

BSPI0

TIM0

BSPI1

TIM1

UART0

TIM2

TIM3

UART1/SC

APB bus

APB bus

UART2

RTC

UART3

XTI

USB

WDG

CAN

GPIO0

HDLC

GPIO1

GPIO2

STR71x

General Purpose Input/Output(GPIO)

GPIO0

GPIO1

GPIO2


Gpio features
GPIO Features

  • Up to 48 multifunction bi-directional I/O ports available :

    • 40 Standard I/Os (sink up to 4mA)

    • 8 High Current I/Os (P2.0 - P2.7 can sink up to 8mA)

    • 4 Analog Inputs (P1.0 - P1.3)

    • Alternate Functions pins (for Timers, UART, SPI, CAN, USB and I2C)

    • 14 I/Os can be set-up as Wake-Up and Interrupt input

  • Number of I/O ports depending on the chip package :

    • STR710 : 48 I/O ports

    • STR711 : 30 I/O ports

    • STR712 : 32 I/O ports


Gpio configurations
GPIO Configurations

  • All the I/O ports are individually software configurable using 3 registers :

    • PC0 : Configuration Register 0

    • PC1 : Configuration Register 1

    • PC2 : Configuration Register 2

  • The data port is a 16-bit register :

    • PD : Data Register


Gpio logic structure

Alternate Function (IN)

Analog Input

to On-chip Peripherals

Input Latch

I/O Data Register

TTLCMOS

Read/Write

I/O pin

Output Latch

Push-PullTristate

Open DrainWeak Push-Pull

from On-chip Peripherals

Alternate Function (OUT)

GPIO Logic Structure


Gpio programming tips
GPIO Programming Tips

  • A/D conversion

    • Each pin used by the ADC12 cell must be configured as High impedance Analog input

  • Alternate function

    • Each pin used as output or input/output alternate function must be set to AlternateFunctionPush Pull or Alternate Function Open Drain (example: Timer output compare, UART Tx, …)

    • Each pin used as input alternate function must be set to input tristate to avoid any internal conflict (example: UART Rx)

  • Open Drain Outputs

    • Can be used for bus driving where several devices are connected on the same line

    • Can be wired together in parallel to increase current drive capability

  • Data Input/Output

    • Can be used to configure the GPIO port to input with pull-up or pull-down resistor (100 K)

  • Warning

    • The high-level functions operating on less than 16-bit I/O data always perform a 16-bit read-modify-write access that may be interrupted and also cause a data corruption. To avoid this, such portions of code should be placed within critical sections (disable/enable interrupts locally).


Gpio programming example
GPIO Programming Example

This example shows how to configure the I/O port pins.

Configuration Steps

Programming Steps

{

GPIO_Config(GPIO0, 0x00FF, GPIO_OUT_PP);

  • Configure P0.0:P0.7 as Push-Pull Output

  • Set P0.0:P0.7 to high level

GPIO_ByteWrite(GPIO0, GPIO_LSB, 0xFF);

  • Configure P0.8 as TTL Input

GPIO_Config(GPIO0, 1<<8, GPIO_IN_TRI_TTL);

  • Configure P0.10:P0.11 as Alternate Function Push-Pull

GPIO_Config(GPIO0, 0x0C00, GPIO_AF_PP);

  • Configure P1.13 as Open Drain Output

GPIO_Config(GPIO1, 1<<13, GPIO_OUT_OD);

  • Configure P1.15 as Wake-Up and Interrupt inputs

GPIO_Config(GPIO1, 0x8000, GPIO_INOUT_WP);

}


Str71x peripherals inter integrated circuit i c
STR71x PeripheralsInter-Integrated Circuit(I²C)


Inter integrated circuit i c

ARM7TDMI

CPU

EMI

PRCCU

FLASH

JTAG

ARM7 native bus

RAM

APB1

APB2

I2C0

ADC12

I2C0

I2C1

EIC

I2C1

BSPI0

TIM0

BSPI1

TIM1

UART0

TIM2

TIM3

UART1/SC

APB bus

APB bus

UART2

RTC

UART3

XTI

USB

WDG

CAN

GPIO0

HDLC

GPIO1

GPIO2

STR71x

Inter-Integrated Circuit (I²C)


I c features
I²C Features

  • Two I²C interfaces :

    • I2C0 multiplexed with HDLC

    • I2C1 multiplexed with BSPI0

  • Controls all I²C bus specific sequencing, protocol, arbitration and timing

  • Multi Master and slave capability

  • Standard and fast I²C mode (up to 400kHz)

  • 7-bit and 10-bit addressing


I c block diagram

Control Register

Control Logic

Data Register

Status Registers 1 & 2

Data Control

SDA

SDA

Data Shift Register

Comparator

Own Address Registers 1 & 2

Clock Control

SCL

SCL

Clock Control Register

Ext. Clock Control Register

Control Register

Control Logic

Status Registers 1 & 2

Clock Control

Comparator

Interrupt

Interrupt

Clock Control Register

Own Address Registers 1 & 2

Ext. Clock Control Register

I²C Block Diagram

  • 2 bidirectional lines

  • Standard and fast I²C mode (up to 400kHz)

  • 7-bit and 10-bit addressing

  • Interrupt generation

  • End-of-byte transmission flag

  • End-of-address transmission flag

  • Error detection flags


I c clock control

2 registers control the clock :

Clock Control Register (CCR)

Extended Clock Control Register (ECCR)

Configuration depending on speed(Standard/Fast)

Standard mode (FM/SM=0): FSCL ≤ 100kHz

Fast mode (FM/SM=1): 100kHz < FSCL< 400kHz

I²C Clock Control

[CC11..CC0] = (FAPB1 / 2 FSCL) - 7

[CC11..CC0] = (FAPB1 / 3 FSCL) - 9


I c programming example

SR2

SR2

7

7

6

6

5

5

4

4

3

3

2

2

1

1

0

0

-

-

-

-

ENDAD

1

AF

AF

STOPF

STOPF

ARLO

ARLO

BERR

BERR

GCAL

GCAL

SR1

SR1

7

7

6

6

5

5

4

4

3

3

2

2

1

1

0

0

EVF

EVF

ADD10

ADD10

TRA

TRA

BUSY

BUSY

BTF

BTF

ADSL

ADSL

M/SL

M/SL

SB

1

DR

DR

DR

DR

7

7

7

7

6

6

6

6

5

5

5

5

4

4

4

4

3

3

3

3

2

2

2

2

1

1

1

1

0

0

0

0

x

1

D7

D7

x

D6

0

D6

D5

D5

0

x

1

x

D4

D4

D3

0

D3

x

x

D2

D2

0

D1

D1

x

0

x

D0

D0

0

ECCR

ECCR

CCR

CCR

7

7

6

6

5

5

4

4

3

3

2

2

1

1

0

0

7

7

6

6

5

5

4

4

3

3

2

2

1

1

0

0

-

-

-

-

-

-

CC11

0

CC10

0

CC9

0

0

CC8

1

CC7

F/SM

0

CC6

0

CC5

0

1

CC4

CC3

1

0

CC2

0

CC1

CC0

1

CR

CR

CR

CR

CR

7

7

7

7

7

6

6

6

6

6

5

5

5

5

5

4

4

4

4

4

3

3

3

3

3

2

2

2

2

2

1

1

1

1

1

0

0

0

0

0

-

-

-

-

-

-

-

-

-

-

PE

1

PE

0

PE

ENGC

ENGC

ENGC

ENGC

ENGC

START

START

START

START

1

ACK

ACK

ACK

ACK

ACK

STOP

STOP

1

STOP

STOP

ITE

ITE

ITE

ITE

ITE

OAR2

OAR2

7

7

6

6

5

5

4

4

3

3

2

2

1

1

0

0

1

FR2

0

FR1

1

FR0

-

-

-

-

ADD9

ADD9

ADD8

ADD8

-

-

I²C Programming Example

This example shows how to use the I2C0 cell as a master transmitter in the 7-bit addressing mode.

Configuration Steps

Programming Steps

{

I2C_Init (I2C0);

  • Initialize the I2C0 interface

  • Configure the interface delays

I2C_FCLK_Config (I2C0);

  • Configure SCL and SDA I/Os as AF Open Drain

GPIO_Config (GPIO1, I2C0_SCL| I2C0_SDA, GPIO_AF_OD);

  • Enable the I2C interface

I2C_OnOffConfig (I2C0, ENABLE);

  • Configure interface speed

I2C_SpeedConfig (I2C0, 100000);

  • Generate the START Condition

I2C_STARTGenerate (I2C0, ENABLE);

  • Wait until SB flag is set then clear it

while (!(I2C_FlagStatus (I2C0, DIRECT, I2C_SB));

  • Send Slave Address

I2C_AddressSend (I2C0, 0x90, I2C_Mode7, I2C_TX);

  • Wait until ENDAD flag is set then clear it

while (!(I2C_FlagStatus (I2C0, DIRECT, I2C_ENDAD));

I2C_FlagClear (I2C0, I2C_ENDAD);

  • Send byte to slave

I2C_ByteSend (I2C0, 0x09);

  • Generate Stop Condition

I2C_STOPGenerate (I2C0, ENABLE);

  • Disable I2C interface

I2C_OnOffConfig (I2C0, DISABLE);

}

!

Don’t forget to configure the GPIO1 port pins as Alternate Function Open Drain


Str71x peripherals buffered serial peripheral interface bspi
STR71x PeripheralsBuffered Serial Peripheral Interface (BSPI)


Buffered serial peripheral interface bspi

ARM7TDMI

CPU

EMI

PRCCU

FLASH

JTAG

ARM7 native bus

RAM

APB1

APB2

I2C0

ADC12

I2C1

EIC

BSPI0

TIM0

BSPI0

BSPI1

TIM1

BSPI1

UART0

TIM2

TIM3

UART1/SC

APB bus

APB bus

UART2

RTC

UART3

XTI

USB

WDG

CAN

GPIO0

HDLC

GPIO1

GPIO2

STR71x

Buffered Serial Peripheral Interface (BSPI)


Bspi features
BSPI Features

  • Two interfaces :

    • BSPI0 multiplexed with I2C1 and UART3

    • BSPI1

  • Programmable FIFO depth up to two 10-word *16-bit

  • Operate with 8- or 16-bit word length

  • Interrupts generation for receive and transmit events

  • Master and Slave modes support


Bspi block diagram

Data

Bus

Transmit FIFO

10 x 16-bit

Transmit FIFO

10 x 16-bit

16

Data

Bus

16

Pin

Control Logic

Pin

Control Logic

Shift Register

MISO

Slave

Slave

Master

Master

MOSI

16

Master

Master

Slave

Slave

SCK

Receive FIFO

10 x 16-bit

Receive FIFO

10 x 16-bit

16

/SS

CLK

CLK

16

CLK

BSPI

Control Logic

BSPI

Control Logic

Slave

Slave

Master

Master

CSR1

16

CSR2

CSR1

16

CSR2

BSPI Block Diagram

  • 2 FIFOs : Transmit and Receive

  • 16-bit bus

  • 16-bit shift register

  • Internal clock

  • Pin control logic

  • 2 control/status registers

Shift Register


Bspi programming example

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

BSPITXR

BSPITXR

15

15

14

14

13

13

12

12

11

11

10

10

9

9

8

8

7

7

6

6

5

5

4

4

3

3

2

2

1

1

0

0

BSPICSR1

BSPICSR1

BSPICSR1

BSPICSR1

BSPICSR1

BSPICSR1

BSPICSR2

BSPICSR2

BSPICLK

BSPICLK

15

15

15

15

15

15

14

14

14

14

14

14

13

13

13

13

13

13

12

12

12

12

12

12

11

11

11

11

11

11

10

10

10

10

10

10

9

9

9

9

9

9

8

8

8

8

8

8

7

7

7

7

7

7

6

6

6

6

6

6

5

5

5

5

5

5

4

4

4

4

4

4

3

3

3

3

3

3

2

2

2

2

2

2

1

1

1

1

1

1

0

0

0

0

0

0

TX[15:0]

TX[15:0]

15

15

14

14

13

13

12

12

11

11

10

10

9

9

8

8

7

7

6

6

5

5

4

4

3

3

2

2

1

1

0

0

15

15

14

14

13

13

12

12

11

11

10

10

9

9

8

8

7

7

6

6

5

5

4

4

3

3

2

2

1

1

0

0

RFE[3:0]

RFE[3:0]

RFE[3:0]

RFE[3:0]

RFE[3:0]

RFE[3:0]

1 1

WL[1:0]

WL[1:0]

WL[1:0]

WL[1:0]

WL[1:0]

CPHA

1

CPHA

1

CPHA

1

1

CPOL

CPOL

1

CPOL

CPOL

BEIE

BEIE

BEIE

BEIE

BEIE

BEIE

-

-

-

-

-

-

-

-

-

-

-

-

REIE

REIE

REIE

REIE

REIE

REIE

RIE[1:0]

RIE[1:0]

RIE[1:0]

RIE[1:0]

RIE[1:0]

RIE[1:0]

1

1

MASTER

MASTER

1

1

1

1

BSPE

1

1

1

TIE[1:0]

TIE[1:0]

TFE[3:0]

TFE[3:0]

TFNE

TFNE

TFF

TFF

TUFL

TUFL

TFE

TFE

ROFL

ROFL

RFF

RFF

RFNE

RFNE

BERR

BERR

-

-

DFIFO

DFIFO

-

-

DIV[7:0]

DIV[7:0]

TIE[1:0]

0

0

1

0

TFNE

TFF

TUFL

TFE

ROFL

RFF

RFNE

BERR

-

DFIFO

-

0

0

1

0

0

0

0

0

BSPI Programming Example

This example shows how to use the BSPI1 cell as a master and transmit three words.

Programming Steps

Configuration Steps

{

BSPI_Init(BSPI1);

  • Initialize the BSPI1

  • Configure interface speed

BSPI_ClockDividerConfig (BSPI1, 0x20);

  • Configure the I/Os as Alternate Function Push-Pull

GPIO_Config (GPIO0, 0x0070, GPIO_AF_PP);

  • Enable the BSPI1 interface

BSPI_Enable (BSPI1, ENABLE);

  • Select master mode

BSPI_MasterEnable (BSPI1, ENABLE);

  • Configure the clock as active high

BSPI_ClkActiveHigh(BSPI1, ENABLE);

  • Enables capturing the first data sample on the first edge of SCK

BSPI_ClkFEdge(BSPI1, ENABLE);

BSPI_8bLEn(BSPI1, DISABLE);

  • Set the word length to 16 bits

BSPI_TrFifoDepth(BSPI1, 3);

  • Transmit FIFO depth is 3 words

for(i=0; i<3; i++)

BSPI_WordSend(BSPI1, 0x5555);

}

  • Transmit three words of data

!

Don’t forget to configure the GPIO port pins as Alternate Function Push-Pull


Str71x peripherals universal asynchronous receiver transmitter uart
STR71x Peripherals Universal AsynchronousReceiver Transmitter(UART)


Universal asynchronous receiver transmitter uart

ARM7TDMI

CPU

EMI

PRCCU

FLASH

JTAG

ARM7 native bus

RAM

APB1

APB2

I2C0

ADC12

I2C1

EIC

BSPI0

TIM0

BSPI1

TIM1

UART0

TIM2

UART0

TIM3

UART1/SC

UART1/SC

APB bus

APB bus

UART2

RTC

UART2

UART3

XTI

UART3

USB

WDG

CAN

GPIO0

HDLC

GPIO1

GPIO2

STR71x

Universal Asynchronous Receiver Transmitter (UART)


Uart features 1 2
UART Features (1/2)

  • Full duplex, asynchronous communication

  • Two internal FIFOs (16 words deep) for transmit and receive data

  • 16-bit baud rate generator :

    • Baud rate = FAPB1 / (16 × BRR)

  • Programmable word length :

    • 8 bits

    • 9 bits

  • Programmable Stop bits :

    • 0.5 Stop bit

    • 1 Stop bit

    • 1.5 Stop bit

    • 2 Stop bits

  • Noise, overrun and frame error detection

  • Parity control

  • Loop Back

  • UART1 usable in SmartCard mode

  • UART3 multiplexed with BSPI0


Uart features 2 2
UART Features (2/2)

  • Receiver wake-up function by the most significant bit

  • 9 Interrupt sources with flags :

    • Receive Buffer Full

    • Receive Buffer Half Full

    • Overrun error detected

    • Transmitter empty

    • Transmit Buffer Half Empty

    • Parity error

    • Framing Error

    • Timeout idle

    • Timeout Not Empty

  • 1 Flag without interrupt

    • Transmit Buffer Full


Uart serial data format

8-bit Data frame

1st Stop bit

2nd Stop bit

8th bit

Start

D 0

D 1

D 2

D 3

D 4

D 5

D 6

  • Data Bit (D7) (8-bit data mode)

  • Parity bit (7-bit data + parity mode)

9-bit Data frame

2nd Stop bit

1st Stop bit

Start

D 0

D 1

D 2

D3

D 4

D 5

D 6

D 7

9th bit

  • Data Bit (D8) (9 bit data mode)

  • Parity bit (8-bit data + parity mode)

  • Wake-Up bit (8-bit data + wake-up mode)

UART Serial Data Format

  • 8-bit word length

  • 9-bit word length


Uart timeout mechanism
UART Timeout Mechanism

  • The Timeout counter reloads the TOR register content whenever :

    • The Rx Buffer is read

    • The UART starts to receive a character

    • The TOR is written

  • The TimeoutNotEmpty flag is set when the RxFIFO is not empty and the timeout counter is zero

    • Used to avoid data overrun

  • The Timeoutidle flag is set if the RxFIFO is empty and the Timeout counter reaches zero

    • Used to avoid long wait for data reception


Uart programming example
UART Programming Example

This example shows how to configure the UART and send a character.

Configuration Steps

Programming Steps

{

GPIO_Config(GPIO0, UART0_Rx_Pin, GPIO_IN_TRI_CMOS);

GPIO_Config(GPIO0, UART0_Tx_Pin, GPIO_AF_PP);

  • Configure the UART0 Rx and Tx pins

  • Configure the UART0 as follows :

    • 8-bit mode + parity

    • Odd parity

    • 1 Stop bit

    • 9600 bps

UART_Config(UART0, 9600, UART_ODD_PARITY, UART_1_StopBits, UART_8D_P);

UART_FifoConfig(UART0, ENABLE);

  • Enable FIFOs

  • Disable Loop Back

UART_LoopBackConfig(UART0, DISABLE);

  • Enable Rx

UART_RxConfig(UART0, ENABLE);

  • Choose and Enable Interrupts

UART_ItConfig(UART0, UART_RxBufFull, ENABLE);

  • Turn UART0 on

UART_OnOffConfig(UART0, ENABLE);

  • Send a character

UART_ByteSend(UART0, pCharToSend);

}

!

Don’t forget to configure the GPIO port pins


Str71x peripherals universal serial bus usb
STR71x PeripheralsUniversal Serial Bus(USB)


Universal serial bus usb

ARM7TDMI

CPU

EMI

PRCCU

FLASH

JTAG

ARM7 native bus

RAM

APB1

APB2

I2C0

ADC12

I2C1

EIC

BSPI0

TIM0

BSPI1

TIM1

UART0

TIM2

TIM3

UART1/SC

APB bus

APB bus

UART2

RTC

UART3

XTI

USB

WDG

CAN

GPIO0

HDLC

GPIO1

GPIO2

STR71x

Universal Serial Bus(USB)

USB


Usb features
USB Features

  • USB 2.0 Full Speed (12 Mbit/s)

  • Configurable number of endpoints

    • up to 16 mono-directional / single buffered endpoints

    • up to 8 double buffered endpoints

  • Isochronous transfers support

  • Double-buffered bulk endpoint support

  • USB Suspend/Resume operations


Usb block diagram

D-

D+

Control

Registers & Logic

PLL

Analog

Transceiver

Interrupt

Registers & Logic

48 MHz

USB IP

Control

Registers & Logic

RX-TX

RX-TX

Clock

Recovery

Clock

Recovery

Suspend

Timer

Control

Control

Interrupt

Registers & Logic

Endpoint

Selection

Endpoint

Selection

SIE

SIE

Packet

Buffer

Interface

Endpoint

Registers

Endpoint

Registers

Endpoint

Registers

Endpoint

Registers

APB Interface

Register

Mapper

Interrupt

Mapper

Packet

Buffer

Memory

Arbiter

APB Interface

APB Wrapper

PCLK1

APB bus

Interrupt lines

USB Block Diagram

  • S.I.E. : Serial Interface Engine

    • NRZI encoding/decoding

    • Synchronization pattern recognition

    • Bit stuffing

    • CRC generation/checking

    • PID verification/generation

    • Handshake evaluation

    • Generate signals according to USB cell and endpoints related events (e.g. correct transfer event).

Suspend

Timer

  • Control and interrupt registers for S.I.E. control and interrupt generation

  • Endpoint registers for endpoints configuring

  • Suspend timer: detects a global suspend when no traffic received for 3 ms

  • APB interface

    • Interface to the APB1 bus

    • Provides a packet buffer memory which contains the endpoints received and/or packets to be transmitted.


Usb software library

Application

(main.c, 71x_it.c, eic.c...)

Device Properties (usb_prop.c)

Device Descriptors

(usb_desc.c)

USB interrupts handlers

(usb_istr.c)

Protocol Management Layer (usb_core.c)

USB library main files

Hardware Abstraction Layer

(usb_regs.c)

USB Software Library

USB application template files


Str71x peripherals controller area network can
STR71x PeripheralsController Area Network(CAN)


Controller area network can

ARM7TDMI

CPU

EMI

PRCCU

FLASH

JTAG

ARM7 native bus

RAM

APB1

APB2

I2C0

ADC12

I2C1

EIC

BSPI0

TIM0

BSPI1

TIM1

UART0

TIM2

TIM3

UART1/SC

APB bus

APB bus

UART2

RTC

UART3

XTI

USB

WDG

CAN

GPIO0

HDLC

GPIO1

GPIO2

STR71x

Controller Area Network(CAN)

CAN


Can features
CAN Features

  • Supports CAN protocol versions 2.0 A and 2.0 B (active)

  • Bit rates up to 1 Mbit/s

  • 32 configurable message objects

  • Acceptance filtering available for each message object

  • Maskable interrupts

  • Programmable FIFOs of any depth (up to 32 messages)

  • 5 operating modes including test modes


Can block diagram

CAN_TX

CAN_RX

CAN Core

Message Handler

Message RAM

Registers

Interrupt

Module Interface

Data IN

Control

Data OUT

Address[7:0]

CAN Block Diagram

  • Core

    • Protocol handling and communication with the CAN bus

CAN Core

  • Message RAM

    • Storage of message objects and identifier masks

Message Handler

Message RAM

  • Message handler

    • State machine that controls data exchange and interrupts generating

Registers

  • Registers

    • Contain setup, control and status

Module Interface

  • Module interface

    • Connect the cell to the internal bus


Can operating modes

Normal

Full usage of the message RAM

32 message objects

Acceptance filtering

Prioritized message handling

Full usage of registers

Suitable for complex devices

Basic

Message RAM is not used

2 message objects (1 TX + 1 RX)

No acceptance filtering

No priority handling

Restricted registers and flags

Suitable for simple devices (passive)

CAN Operating Modes


Can test modes

Silent

CAN RX

CAN TX

CAN RX

CAN TX

CAN TX

CAN RX

=1

=1

TX

RX

TX

TX

RX

RX

CAN Core

CAN Core

CAN Core

CAN Test Modes

  • Loopback

  • Loopback + Silent

  • Transmission is looped to RX internally

  • Allow host self-test

  • Node is disconnected from the CAN bus

  • Transmission is looped to RX internally

  • Reception remains possible

  • CAN TX is held recessive

  • Transmission is looped to RX internally

  • Transmission remains possible

  • CAN RX is ignored


Can programming tips timing considerations

Nominal Bit Time, Ntq = 12

Sync

Seg

Phase Seg2

Prop Seg

Phase Seg1

TSEG1 = (Sample Point Position) - 1

t

TSEG2 = Ntq - (Sample Point Position)

tq

TSEG1: Time Segment before the sampling point

TSEG2: Time Segment after the sampling point

SJW : Synchronization Jump Width

BRP : Baud Rate Prescaler

Time Quantum

1

BRP

TSEG2

TSEG1

Bit Time

fsys

Bit Time =

tq =

BRP =

x

Bit Rate

fsys

Sampling Point

2

Ntq

CAN Programming TipsTiming Considerations

  • From specific timing parameters :

    • CAN_SetTiming(TSEG1, TSEG2, SJW, BRP); // set a custom timing mode

  • The bitrate can be set up by two ways :

  • From a list of standard values :

    • CAN_SetBitrate(CAN_BITRATE_1M); // choose 1 Mbit/s


Can programming example polling mode
CAN Programming ExamplePolling Mode

The following example shows how to send and receive a data frame in test mode by polling the CAN status.

Configuration Steps

Programming Steps

{

canmsg RxCanMsg;

canmsg TxCanMsg= { CAN_STD_ID, 0x123, 4, { 0x01, 0x02, 0x04, 0x08 } };

  • Declare RX and TX messages

  • Configure CAN RX pin as Input Tristate CMOS

  • Configure CAN TX pin as Alternate Function Push-Pull

  • Initialize the CAN at standard baudrate 100 kbit/s

GPIO_Config(GPIO1, 1<<11, GPIO_IN_TRI_CMOS);

  • Enter the test mode : loopback combined with silent (self-test)

GPIO_Config(GPIO1, 1<<12, GPIO_AF_PP);

CAN_Init(0, CAN_BITRATE_100K);

  • Invalidate all the message objects

CAN_EnterTestMode(CAN_TST_LBACK | CAN_TST_SILENT);

  • Configure the message object 0 as TX with standard identifiers

CAN_InvalidateAllMsgObj();

CAN_SetTxMsgObj(0, CAN_STD_ID);

  • Configure the message object 1 as RX with standard identifiers

CAN_SetRxMsgObj(1, CAN_STD_ID, 0, CAN_LAST_STD_ID, TRUE);

  • Send a data frame using the message object 0

(void)CAN_SendMessage(0, &TxCanMsg);

  • Wait until the transmission is finished

CAN_WaitEndOfTx();

  • Receive the data frame using the message object 1

while (!CAN_ReceiveMessage(1, FALSE, &RxCanMsg)) {}

  • Release the message object 0

CAN_ReleaseTxMessage(0);

CAN_ReleaseRxMessage(1);

  • Release the message object 1

CAN_LeaveTestMode();

}

  • Leave the test mode (switch back to normal)

!

Don’t forget to configure the GPIO1 pins as Input Tristate and AF Push-Pull


Can programming example interrupt mode 1 2
CAN Programming ExampleInterrupt Mode (1/2)

The following example shows how to send and receive a data frame in test mode by setting an interrupt handler.

Configuration Steps

Programming Steps

{

canmsg RxCanMsg;

canmsg TxCanMsg = { CAN_EXT_ID, 0x12345678, 8, { 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17 };

  • Declare RX and TX messages

  • Enable the IRQ generation for the CAN

  • Set the IRQ channel priority to 1

EIC_IRQChannelConfig(CAN_IRQChannel, ENABLE);

  • Enable the interrupts globally

EIC_IRQChannelPriorityConfig(CAN_IRQChannel, 1);

  • Initialize the CAN at standard baudrate 100kbit/s with interrupts enabled

EIC_IRQConfig(ENABLE);

  • Enter the test mode : loopback combined with silent (self-test)

CAN_Init(CAN_CTL_IE, CAN_BITRATE_100K);

CAN_EnterTestMode(CAN_TST_LBACK | CAN_TST_SILENT);

  • Invalidate all the message objects

CAN_InvalidateAllMsgObj();

  • Configure the message object 0 as TX with extended identifiers

CAN_SetTxMsgObj(0, CAN_EXT_ID);

  • Configure the message object 1 as RX with extended identifiers

CAN_SetRxMsgObj(1, CAN_EXT_ID, 0, CAN_LAST_EXT_ID, TRUE);

  • Send a data frame using the message object 0

(void)CAN_SendMessage(0, &TxCanMsg);

… (see next slide)

  • Handle the reception in the interrupt routine

CAN_LeaveTestMode();

  • Leave the test mode (switch back to normal)

EIC_IRQConfig(DISABLE);

}

  • Disable the interrupts globally


Can programming example interrupt mode 2 2
CAN Programming ExampleInterrupt Mode (2/2)

This is the interrupt handler part of the example (contained in the 71x_it.c file).

Configuration Steps

Programming Steps

void CAN_IRQHandler (void)

{

  • Update the CAN_IRQHandler function

  • Get the message object number that made the interrupt occur

int msgobj = CAN->INTR - 1;

if (msgobj >= 0 && msgobj <= 31)

{

  • Test its validity

switch (msgobj)

{

case 0:

  • Handle the case of the message object 0

CAN_ReleaseTxMessage(msgobj);

break;

  • Release the transmit message object

case 1:

  • Handle the case of the message object 1

  • Receive the message contents using the message object 1, and release it

CAN_ReceiveMessage(msgobj, TRUE, &RxCanMsg);

break;

default:

CAN_ReleaseMessage(msgobj);

}

}

}

  • By default, release the message object


Str71x peripherals high level data link controller hdlc
STR71x PeripheralsHigh-Level Data Link Controller(HDLC)


High level data link controller hdlc

ARM7TDMI

CPU

EMI

PRCCU

FLASH

JTAG

ARM7 native bus

RAM

APB1

APB2

I2C0

ADC12

I2C1

EIC

BSPI0

TIM0

BSPI1

TIM1

UART0

TIM2

TIM3

UART1/SC

APB bus

APB bus

UART2

RTC

UART3

XTI

USB

WDG

CAN

GPIO0

HDLC

GPIO1

GPIO2

STR71x

High-Level Data Link Controller (HDLC)

HDLC


Hdlc features

Automatic flag detection and insertion

Automatic zero bit deletion and insertion

Automatic Frame Check Sequence (FCS) generation and check

Abort/Idle detection and transmission

32 Maskable Private Address bits field recognition

4 single-byte Maskable Group Address field recognition

Up to 16-bit programmable preamble/postamble sequences

Check of the number of bytes received in a frame

Capability to complement input/output frames

2 independent input clock lines (reception + transmission)

NRZ, NRZI, FM0, and Manchester codes in both RX/TX

Digital Phase Locked Loop (DPLL) for clock recovery

2 x 128 bytes RAM buffers for transmission and reception

4 operating modes :

Local loopback

Autoecho

Full Duplex

Interrupt

Multiplexed with I2C0

HDLC Features

Refer to the Reference Manual for further details


Str71x peripherals smartcard interface
STR71x PeripheralsSmartCard Interface


Smartcard interface

ARM7TDMI

CPU

EMI

PRCCU

FLASH

JTAG

ARM7 native bus

RAM

APB1

APB2

I2C0

ADC12

I2C1

EIC

BSPI0

TIM0

BSPI1

TIM1

UART0

TIM2

TIM3

UART1/SC

APB bus

APB bus

UART2

RTC

UART3

XTI

USB

WDG

CAN

GPIO0

HDLC

GPIO1

GPIO2

STR71x

SmartCard Interface

UART1/SC


Smartcard features
SmartCard Features

  • ISO7816-3 asynchronous protocol support

  • 16-bit counter

  • Separate clock generator

  • Configurable clock prescaler value

  • Access through UART1 set up to SmartCard mode


Smartcard protocol

11 ETU

Parity

bit

D7

Start

D 0

D 1

D 2

D 3

D 4

D 5

D 6

Line pulled low by receiver during stop in case of parity error

SmartCard Protocol

  • ISO7816-3 asynchronous protocol



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