Computer System Session 5

1. Computer SystemSession 5 Andreas U Kuswara

2. Agenda Combinational Logic Design Procedure Adders Subtractors Analysis Procedure Multilevel Logic Circuit Project Explanation Group Formation Reading Mano: Ch 4 Project #1 Objectives Understand the nature of Combinational Logic Understand and able to execute the combinational logic design procedure Session Profile

3. Combinational Logic • Combinational Logic is a logical circuit consists of logic gates whose outputs at any time are determined directly from the present combination of inputs without regard to previous inputs

4. Common Combinational Logic • Adders • Half-Adders • Full-Adders • Substractors • Half-Substractors • Full-Substractors

5. Adders • One of the basic arithmetic process in computer system • One that performs the addition of 2 bits is Half – Adder • One that performs the addition in 3 bits (2 significant bits and a previous carry) is called Full – Adder

6. Half-Adder • 2 Input & 2 output • The truth table • Thus the Boolean function is • S = x’y + xy’ • C = xy • The function cannot be further simplified • The Logic Gate is drawn

7. S = x’y + xy’ C = xy S = x  y C = xy S = (x+y)(x’+y’) C = xy Half-Adder Implementations

8. Full –Adder • 3 Input (x & y as the input and z as the previous carry) & 2 output • The truth table

9. Full –Adder • K-Map to simplify • The Boolean function is: • S = x’y’z + x’yz’ + xy’z’ + xyz • C = xy + xz + yz

10. Full –Adder • The Logic Gate is drawn • S = x’y’z + x’yz’ + xy’z’ + xyz • C = xy + xz + yz

11. Subtractors • One of the basic arithmetic process in computer system • One that subtracts 2 and produce their difference is Half-Substractor • One that subtracts 2 and produce their difference while taking account that 1 have been borrowed by a lower significant stage. it is called Full-Substractor

12. Half-Substractor • 2 Input & 2 output (Borrow & Data) • The truth table • Boolean Function cannot be simplified • D = x’y + xy’ • B = x’y

13. Full-Substractor • You do it • Truth table • Simplify with K-Map • Draw the Logic Gate

14. x’y + x’z + yz D = x’y’z + x’yz’ + xy’z’ + xyz Full-Substractor B =

15. Design Procedure • Problem is stated • Number of available input and required output is determined • Input and output are assigned letter symbol • Truth table is derived to show relationships among variables (including don’t care) • Simplified Boolean function is obtained • Logic diagram is drawn

16. 1.Problem is stated • We wish to design a Code Conversion Logic from BCD (Binary Coded Decimal) to Excess-3 Code • The Converter may act as an interface for 2 different data communication system

17. 2.Input & output Determined • The input lines will supply BCD input • BCD is a 4 bit binary system • 4 bits • The output lines should produce Excess-3 Code output • Excess-3 is a 4 bit binary system • 4 bits

18. 3.Letter Symbol Assigned • Input: BCD (A, B, C, D) • Output: Excess-3 (W, X, Y, Z)

19. 4. Truth Table is Derived

20. D’ 5.Simplify Boolean Function • For output Z • Z =

21. CD + C’D’ 5.Simplify Boolean Function • For output Y • Y =

22. B’C + B’D + BC’D’ 5.Simplify Boolean Function • For output X • X =

23. A + BC + BD 5.Simplify Boolean Function • For output W • W =

24. Simplified Boolean Function Z = D' Y = CD + C'D' X = B'C + B'D + BC'D' W = A + BC + BD Implementation Equation Z = D' Y = CD + (C+D)’ X = B‘(C+D) + B (C+D)’ W = A + B(C+D) 6.Draw Logic Diagram

25. 6.Draw Logic Diagram D’ (C+D)’+CD CD (C+D)’ (C+D)’B C+D (C+D)’B+(C+D)B’ (C+D)B’ B’ (C+D)B (C+D)B+A

26. Consideration in Design • Minimum number of gates • Minimum number of input to a gate • Minimum propagation time of signal through circuit • Minimum number of interconnections • Limitation of the driving capabilities of each gates

27. Propagation #1 • Propagation Delay is the average transition delay time for the signal to propagate from input to output • The total propagation delay determined by the amount of gates passed through

28. Propagation #2

29. Analysis Procedure • The “analysis” is the reverse of “design” • Make sure that it is a combinational and not a sequential. Indicated by No Feedback loop. • Proceed to create Boolean Function or Truth Table. If Boolean function is supplied, the K-Map can be directly derived. • The simplified Boolean function can then be written down.

30. Multilevel Logic Circuit #1 • Universal Gate (NAND) • NAND is called Universal Gate, because it can derived all gate with NAND gate.

31. Multilevel Logic Circuit #2 • To obtain a multilevel NAND diagram from a Boolean Expression: • Draw the Logic Diagram • F = A + (B’ + C)(D’ + BE’)

32. Multilevel Logic Circuit #3 • Convert all AND gates to NAND gates with AND invert graphic symbol

33. Multilevel Logic Circuit #4 • Convert all OR gates to NAND gates with Invert OR graphic symbol • Check all small circle in the diagram

34. AdministrativeProject #1 Explanation #1 • Each group will construct a basic Arithmetic Logical Unit (ALU) that can execute the following operation: • Option 1: Adder & Subtractor (4 groups) • Option 2: Multiplier (4 groups)

35. AdministrativeProject #1 Explanation #2 • The ALU must be able to do the desired arithmetic operation using both decimal and hexadecimal numbers (4-bit). • Hint: The ALU will have a selector bit that will decide weather the input is a decimal or hexadecimal.

36. AdministrativeProject #1 Explanation #3 • Conduct your design steps following this guideline: • Identify the input and output relation • Write the required functions (Boolean expressions) • Simplify and optimized your expression using the Karnough-Map • Write the simplified functions (Boolean expressions) • Implement your design using the appropriate gates and draw the designs (you may use the appropriate logic gate IC, e.g. AND, OR, NAND, NOR, XOR) • Build & test your design on a proto-board powered by a batteries or Dc-adapter • Do necessary adjustments

37. AdministrativeProject #1 Explanation #4 • Document all the steps in a report and prepare a presentation of the steps done, problems encountered and steps taken to overcome them, the test results and demonstration of the construction. • Due: Session 7 (design presentation: 5%)

38. Group 1 Willy Ignatius David Option 1/Option 2 Group 2 Probo Erik Steraldy Option 1/Option 2 Group 3 Albertus Bondan Seno Option 1/Option 2 Group 4 Errol Anton Yurike Option 1/Option 2 AdministrativeGroup Formation #1

39. Group 5 Lena Shierly Maria Option 1/Option 2 Group 6 Made Bima Johny Sandra Option 1/Option 2 Group 7 Enrico William Leo Option 1/Option 2 Group 8 Yusar Kristianto Fritz Option 1/Option 2 AdministrativeGroup Formation #2