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IN THE NAME GOD. Advanced VLSI Class Presentation A 1.1GHz Charge Recovery Logic Insructor : Dr. Fakhrayi Presented by : Mahdiyeh Mehran. Adopted From: A 1.1GHz Charge Recovery Logic. Visvesh S. Sathe Juang-Ying Chueh Marios C. Papaefthymiou University of Michigan, Ann Arbor, USA.

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IN THE NAME GOD

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In the name god

IN THE NAME GOD

Advanced VLSI Class PresentationA 1.1GHz Charge Recovery Logic

Insructor : Dr. Fakhrayi

Presented by : Mahdiyeh Mehran


Adopted from a 1 1ghz charge recovery logic

Adopted From:A 1.1GHz Charge Recovery Logic

Visvesh S. Sathe

Juang-Ying Chueh

Marios C. Papaefthymiou

University of Michigan, Ann Arbor, USA


Contributions

Contributions

  • First ever demonstration of fully integrated charge-recovery chip in 0.13mm CMOS at GHz clock rates

    • Boost Logic : Dynamic charge-recovery circuit family

  • Chain of test gates (1600 gates total)

  • Integrated inductor and clock generator

  • Resonant operation at 850MHz, 1.3V

  • Functional at 1.1GHz, 1.4V

  • Energy recovery rate at resonance = 60%


Outline

Outline

  • Charge Recovery – Brief overview

    • Basic Principles

  • Boost Logic structure

  • Boost Logic operation

  • Boost Logic test chip

  • Chip measurement results


Brief overview of charge recovery

Brief Overview of Charge Recovery

v

Vin

R

I

Vin

Vin

»

+

VC

VC

C

C

-

time

I

time

T

Ref.[1]

  • Gradual transition of power supply (Power-Clock).

  • Supply must enable recovery of charge.

  • Inductor used to resonate power clock.


Outline1

Outline

  • Charge Recovery – Brief overview

    • Basic Principles

  • Boost Logic structure

  • Boost Logic operation

  • Boost Logic test chip

  • Chip measurement results


In the name god

VC = Vdd’ – Vss’ = Vth

Vdd’ = (Vdd + Vth)/2

Vss’ = (Vdd - Vth)/2


In the name god

Boost Logic: Hybrid Charge Recovery

out

out

Ref.[1]

  • Two-stage operation : Logic and Boost

  • Logic Stage performs logical evaluation

  • Boost Stage takes output nodes to full rail.


In the name god

Boost Logic: Hybrid Charge Recovery

Ref.[1]

  • Two-stage operation : Logic and Boost

  • Logic Stage performs logical evaluation

  • Boost Stage takes output nodes to full rail.


Ref 1

Boost Logic Structure

Ref.[1]


Outline2

Outline

  • Charge Recovery – Brief overview

    • Basic Principles

  • Boost Logic structure

  • Boost Logic operation

  • Boost Logic test chip

  • Chip measurement results


Boost logic inverter

Boost Logic Inverter

Ref.[1]


In the name god

Boost Logic Operation

f

out

1.2

out

0.6

f

0

t (s)

Logic Stage

Drives Outputs

Ref.[1]

Boost Stage deactivated – all 4 devices in cutoff.

  • Clocked transistors turn on, enabling evaluation.

  • Logic stage drives output nodes to conventional rails.


In the name god

Boost Logic Operation

f

Ref.[1]

  • With f = Vss’ and f = Vdd’ clocked transistors turn off.

  • Boost Stage remains tri-stated from output.

  • Pre-resolved output nodes provided to Boost Stage.

1.2

0.6

f

0

t (s)

Both Stages

Tri-stated


In the name god

Boost Logic Operation

f

out

f

1.2

out

0.6

0

t (s)

Boost Stage

Amplifies Outputs

Ref.[1]

  • As f (f) crosses Vdd’ (Vss’), Boost stage turns on.

  • Transistors M2 and M3 turn on.

  • Outputs track power clock.


In the name god

Boost Logic Operation

f

out

1.2

out

f

0.6

0

t (s)

Boost Stage

Charge Recovery

Ref.[1]

  • As f (f) moves toward Vss(Vdd)

    • Transistors M2 and M3 turn on.

    • Charge in load capacitance returns to resonant clock.

  • As V(out) – V(out) ≈ Vth, all 4 devices are in cutoff.


Cascade simulation

Cascade Simulation

Logic

Boost

(V)

f

1.0

in

0.5

out

out

0

0n

0.5n

1n

t (s)

f

in

i1

i0

Ref.[1]

  • Logic cascaded with alternate clock phases.

  • Vgs’< 0 in logic evaluation trees when off.

  • Low Vth devices desirable in logic evaluation trees.


Outline3

Outline

  • Charge Recovery – Brief overview

    • Basic Principles

    • Previous work

  • Issues with previous charge recovery logic

  • Boost Logic structure

  • Boost Logic operation

  • Boost Logic test chip

  • Chip measurement results


In the name god

Boost Logic Test Chip

Ref.[1]

  • Oscillation driven by reference clock.

  • Programmable clock generator

    • Variable Duty Cycle 0%<D<50%

    • Variable Switch Width 0<W<450µm


In the name god

Boost Logic Test Chip : Die Shot

Clock generator switches

Boost Logic gate chains

Clock generator switches

Programmable

Schmitt triggers

  • Capacitance per phase = 29pF

  • Inductance = 2.4nH (2 layers, Cu, 0.7µm thick)


Outline4

Outline

  • Charge Recovery – Brief overview

    • Basic Principles

    • Previous work

  • Issues with previous charge recovery logic

  • Boost Logic structure

  • Boost Logic operation

  • Boost Logic test chip

  • Chip measurement results


In the name god

Energy/Current Measurements

50

40

Energy

Current

45

35

40

30

Current (mA)

Energy Dissipation per Cycle (pJ)

35

25

Resonant

Frequency

30

20

25

15

0.7

0.8

0.9

1.0

1.1

Operating Frequency (GHz)

Ref.[1]

  • Energy measured for all possible W, D, Vdd and Vc

  • At resonance (850MHz):

    • Energy dissipation in Vdd = 26pJ [40% of CV2]

    • Energy dissipation in VC = 4pJ [VC = 0.45V]


Conclusion

Conclusion

  • First ever charge-recovery test chip to exceed 1GHz clock rate

    • Boost Logic : Dynamic charge-recovery circuit family

  • Fully-integrated clock generator and inductor in 0.13mm CMOS

  • Functional up to 1.1GHz

  • Resonant frequency = 850MHz

  • Energy recovery rate at resonance = 60%


References

References

[1] V. S. Sathe, et al., “A 1.1GHz Charge-Recovery Logic,”ISSCC, pp.388-390, Feb., 2006.

[2] V. S. Sathe, et al., “A GHz-Class Charge Recovery Logic,” ISLPED, pp.91-94, Aug., 2005.

[3] S. Kim, et al., “True Single-Phase Adiabatic Circuitry,” Transactions on VLSI Systems, pp. 52-63, Feb., 2001.

[4] D. Suvakovic, C. Salama, “Two Phase Non-Overlapping Clock Adiabatic Differential Cascode Voltage Switch Logic (ADCVSL),” ISSCC Dig.Tech.Papers, pp. 364-365, Feb., 2000.

[5] D. Maksimovic, V. Oklobdzija, B. Nikolic, and K. Current

“Clocked CMOS Adiabatic Logic with Integrated Single-Phase Power-Clock Supply,”Transactions on VLSI Systems, Aug., 2000.


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