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Center for Embedded Systems Research/ Dept. of Computer Science North Carolina State University

Research Topics Embedded, Real-time, Sensor Systems Frank Mueller moss.csc.ncsu.edu/~mueller mueller@cs.ncsu.edu. Center for Embedded Systems Research/ Dept. of Computer Science North Carolina State University. voltage. 2. 1. current. 3. Ca. Cb. Power-Aware RT Scheduling.

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Center for Embedded Systems Research/ Dept. of Computer Science North Carolina State University

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  1. Research TopicsEmbedded, Real-time, Sensor SystemsFrank Muellermoss.csc.ncsu.edu/~muellermueller@cs.ncsu.edu Center for Embedded Systems Research/ Dept. of Computer Science North Carolina State University

  2. voltage 2 1 current 3 Ca Cb Power-Aware RT Scheduling • EDF-DVS schemes on IBM PowerPC 405LP • Split task based on feedback of avg. exec. time • yield up to 54% reduction in energy • 1-5% energy reduction for async. DVS modulation

  3. Objective: meet deadline Problem: need to know worst-case execution time (WCET) Experimentally: inconclusive We promote static analysis Analyze your execution path Additional benefit: energy savings Dynamic voltage scaling through scheduling Timing Analysis for Real-Time

  4. requirements for cryptographic algo / embedded architectures Experiments mostly uniform cycle overhead for each word size (8/16/32 bits) but differences among classes Parameters that matter: text length, block size, architectural (few) Uniformity  Approximate Model Derive minimum requirements predict performance on new hardware Timing analysis for Sensor Nodes Can be integrated with STI for feedback on integration benefits Tool support for sensor networks w/ real-time constraints Framework (API) for adaptive, low energy security in sensor networks Adaptive Encryption for Sensor Systems

  5. hypothetical simple processor static timing analysis applicable WCET derived assuming the VISA Exploiting performance gain Complex processor typically much faster Exploit newly-created slack Dynamic voltage scaling complex processor @ lower frequency 2 for 1: simple+complex mode in one architecture Energy savings with DVS: 12-47% Speculatively run on complex processor gauge progress (on subtasks) to confirm timeliness if not as timely, switch to simple mode recovery frequency (based on WCETs) speculative frequency (based on PETs) frequency (MHz) frequency requirement VISA: A Virtual Simple Architecture

  6. Overview • Timing analysis framework (ToC’99, JRTS’99/00/01, RTSS’03, RTSS’04) • Toolset predicts max. execution time  scheduling • FAST: Frequency-Aware Timing Analysis (RTSS’03) • VISA: Architecture for Real-Time (ISCA’03,RTSS’04) • Real-time scheduling with dynamic voltage scheduling (LCTES’02, COLP’02, RTAS’04) • Adaptive Encryption for Sensor Systems (CASES’03)

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