Some examples

Lecture 7.3 Paolo PRINETTO Politecnico di Torino (Italy)University of Illinois at Chicago, IL (USA) Paolo.Prinetto@polito.it Prinetto@uic.edu www.testgroup.polito.it Some examples

Goal • This lecture guides the students through the solution of some simple examples of manual synthesis of sequential networks.

Prerequisites • Lectures 7.1 and 7.2

Homework • Students are recommended to try to solve the exercise by themselves, before looking at the proposed solutions.

Further readings • No particular suggestion

Outline • Example #7.3.1: rising edge detector • Example #7.3.2: palindrome string detector • Example #7.3.3: BCD big endian • Example #7.3.4: BCD little endian • Example #7.3.5: parity checker • Example #7.3.6: Ford Thunderbird light controller • Example #7.3.7: code checker • Example #7.3.8: sequence checker

Example #7.3.1: rising edge detector • A circuit is to be designed, having: • An input X • A clock signal CLK, which acts as a proper sampling signal of X, i.e., the frequency of CLK is such that it never happens that two transitions of X occur within a same CLK cycle • An output U, asserted for a clock cycle whenever a rising edge on the input X is detected.

Waveforms CLK X

Waveforms CLK X Z

STG reset H0,0

STG reset 1 H0,0

STG reset 1 L,0 H0,0 0

STG reset 1 0 L,0 H0,0 0

STG reset 1 0 L,0 H0,0 0 1 H1,1

STG reset 1 0 L,0 H0,0 0 1 0 H1,1

STG reset 1 0 L,0 H0,0 0 1 0 H1,1 1

State encoding state encoding H0 00 L 11 H1 10

STT reset 1 0 L,0 H0,0 0 1 0 H1,1 1 state encoding H0 00 L 11 H1 10

STT reset 1 0 x L,0 H0,0 0 y[1:0] • 0 1 • H0  00 11 00 0 • 01 - - 0 • L  11 11 10 0 • H1  10 11 00 1 1 0 H1,1 1 Y[1:0] Z state encoding H0 00 L 11 H1 10

STT x y[1:0] • 0 1 • H0  00 11 00 0 • 01 - - 0 • L  11 11 10 0 • H1  10 11 00 1 Y[1] = x’ + y[0] Y[0] = x’ Z = y[1]y[0]’ Y[1:0] Z

Solution x D[0] y[0] • D[1] = x’ + y[0] • D[0] = x’ • Z = y[1]y[0]’ D Z D[1] y[1] D

Example #7.3.2: palindrome string detector • On a serial transmission line X, bits are transmitted synchronously w.r.t. a clock signal CLK, one bit per clock cycle. • A circuit to be connected to the serial line is to be designed. It has an output U which is asserted whenever the last 4 values got in input forms a palindrome string.

Example #7.3.2: palindrome string detector • On a serial transmission line X, bits are transmitted synchronously w.r.t. a clock signal CLK, one bit per clock cycle. • A circuit to be connected to the serial line is to be designed. It has an output U which is asserted whenever the last 4 values got in input forms a palindrome string. Examples: ANNA – 3993 – 0110

reset - 1 0

reset - 1 0 1 0 1 0 1 0

reset - 1 0 1 0 1 0 1 0 0 0 1 10 11 00 01 1 0 0 1 1

reset - 1 0 1 0 1 0 1 0 0 0 1 10 11 00 01 1 0 0 1 1 1 100 111 000 011 0 0 1 1 0 0 1

reset - 1 0 1 0 1 0 1 0 U=0 0 0 1 10 11 00 01 1 0 0 1 1 1 100 111 000 011 0 0 1 1 0 0 1 0 1 1 0 1001 1111 0000 0110 U=1 1 0 0 1

BCD Example #7.3.3: BCD big endian • On a serial transmission line X, bits are transmitted synchronously w.r.t. a clock signal CLK, one bit per clock cycle. The line is used to transmit groups of 4 bits: each group corresponding to a BCD digit, transmitted MSB first (big endian) • A circuit to be connected to the serial line is to be designed. • It has an output U which is asserted, for 1 clock cycle, in correspondence of the 4th bit of each group, if the group itself is a correct BCD digit.

BCD Solution • When dealing with circuits that must consider groups of bits, it may be convenient to start from a set of states, one for each possible combination of the PO values.

BCD Solution reset A,0 E,1 0 1 1 0

BCD Solution reset A,0 E,1 0 1 1 0 B,0 -

BCD Solution reset A,0 E,1 0 1 1 0 B,0 - C,0 -

BCD Solution reset A,0 E,1 0 1 1 0 B,0 - C,0 - D,0 -

BCD Solution reset A,0 E,1 0 1 1 0 B,0 F,0 - C,0 - D,0 -

BCD Solution reset A,0 E,1 0 1 1 0 B,0 F,0 1 - C,0 H,0 - D,0 -

BCD Solution reset A,0 E,1 0 1 1 0 B,0 F,0 1 - C,0 H,0 - - D,0 I,0 - -

BCD Solution reset A,0 E,1 0 1 1 0 B,0 F,0 1 0 - C,0 G,0 H,0 0 - 1 - D,0 I,0 - -

BCD Example #7.3.4: BCD little endian • Similar to the previous exercise, with the only difference that BCD digits are transmitted LSB first.

BCD Valid Sequences • 0000 0 Y • 0001 8 Y • 0010 4 Y • 0011 12 N • 0100 2 Y • 0101 10 N • 0110 6 Y • 0111 14 N 1000 1 Y 1001 9 Y 1010 5 Y 1011 13 N 1100 3 Y 1101 11 N 1110 7 Y 1111 15 N

BCD reset A,0 E,1   B,0 0 1 F,0 C,0 1  0 D,0 G,0 0 1  E E A

P4 Example #7.3.5: parity checker • On a serial transmission line X, bits are transmitted synchronously w.r.t. a clock signal CLK, one bit per clock cycle. The line is used to transmit strings of 4 bits • A circuit to be connected to the serial line is to be designed. • It has an output Z which is asserted, for 1 clock cycle, in correspondence of the 4th bit of each string, if the string itself contains an odd # of 1’s.

P4 Example • X 0 1 0 0 1 0 1 0 1 1 0 1 0 0 0 0 • Z - - - 1 - - - 0 - - - 1 - -  0

P4 reset B,- C,- even odd

P4 reset B,- C,- 1 1 0 0 even odd D,- E,-

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