1 / 20

Emerging Technologies: A CompSci Perspective

Emerging Technologies: A CompSci Perspective. Tim Sherwood. UC SANTA BARBARA. Software Beware. The End of an Era. $381B / year. The Beginning of a New Era. 3D Stacks of Dies. 80 Cores. Integrated MEMS. The Role of Architecture. Demands. SW. HW. Constraints.

wright
Download Presentation

Emerging Technologies: A CompSci Perspective

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. Emerging Technologies:A CompSci Perspective Tim Sherwood UC SANTA BARBARA

  2. Software Beware

  3. The End of an Era $381B / year

  4. The Beginning of a New Era 3D Stacks of Dies 80 Cores Integrated MEMS

  5. The Role of Architecture Demands SW HW Constraints (Battery Life, Performance, Programmability ) Applications Runtime System Architecture Emerging Technology Circuit Device Package (Noise, Thermal, Yield)

  6. A Simple Performance “Ecosystem” package temp total power dynamic power leakage V communication utilized area freq parallelism feedback OS or runtime No multicore, no spatial variance, no temporal variance, no metrics of cost or error or yield app chip performance

  7. 3D Integration 3D Stacks of Dies 80 Cores Integrated MEMS

  8. 3d technology 5x5μm • Science Fiction? • Intel, IBM, Ziptronix invest heavily in 3d integration research • Many demonstrated 3d prototype systems activelayer ThroughSiliconVias (TSV) CMP Reduced Si Layer Standard Si Substrate

  9. Work at UCSB • Shashidhar Mysore, Banit Agrawal, Sheng-Chih Lin, Navin Srivastava, Kaustav Banerjee and Timothy Sherwood. Introspective 3D Chips , Proceedings of the Twelfth International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), October 2006. San Jose, CA • Gian Luca Loi, Banit Agrawal, Navin Srivastava, Sheng-Chih Lin, Timothy Sherwood, Kaustav Banerjee. A Thermally-Aware Performance Analysis of Vertically Integrated (3-D) Processor-Memory Hierarchy, Proceedings of the 43nd Design Automation Conference (DAC), June 2006. San Francisco, CA

  10. Basic Savings in 3D Area: 4 Dist: √8 ≈ 2.8 Area: 2 Dist: √4 ≈ 2 + 1L Area: 1 Dist: √2 ≈ 1.4 + 3L BW: √8 ≈ 2.8 BW: 4√2 ≈ 5.6 BW: 2√4 ≈ 4 On-chip Latency improvedBandwidth could improve even more UCSB First to Successfully Model Thermal/Performance

  11. Addressing more than Performance • The hardware/software boundary is uniquely situated • Ultimately, Everything is an instruction • Used by Intel, AMD, Freescale, to guide their development • Could Provide Unprecedented Visibility • Not just data capture, we need the ability to put togethera cohesive picture of system interactions and correlate between them in a sound and non-intrusive manner

  12. Cutting Through Abstraction Complex interactions across levels of abstraction make debugging, optimizing, securing, and analysis in general difficult

  13. What programmers want L1_BPU Decode L2_BPU Bus Control Trace CacheTop MOB ITLB Trace Cache Bottom DTLB L1CacheTop L2 Cache UROM FP Exec 2 L1 CacheBottom 320 3 2 FP Reg To Integrated Monitoring Hardware Int Exec MemCtl Alloc Retire 790 Int Reg Rename InstrQ1 Sched InstrQ2 Less buggy systems ($54 Billion / Year ) 32 bit Memory Address 32 bit Memory Value 10 bit Opcodes 2, 5 bit Register Names 2, 32 bit Register Values 10 bits of “status” 4x 4x 4x 4x 4x 4x 3x 3x 3x 3x 3x 3x 1892 bits per cycle = 1 terrabyte/sec @ 4Ghz

  14. Why programmers cant have it L1_BPU Decode L2_BPU Bus Control Trace CacheTop MOB ITLB Trace Cache Bottom DTLB L1CacheTop L2 Cache UROM FP Exec 2 L1 CacheBottom 320 3 2 FP Reg To Integrated Monitoring Hardware Int Exec MemCtl Alloc Retire 790 Int Reg Rename InstrQ1 Sched InstrQ2 • Interconnect is not free • Huge cross chip busses • OptBuf 285um • 20,000 buffers • Analysis is not free • Significant processing required • Extra cost of added heat • $15 budget for cooling • Used by developers

  15. 3D Introspection 5x5μm activelayer Observer PrimaryProcessor CMP Reduced Si Layer Standard Si Substrate

  16. Thermal Impact P4 – Base Case w/ 3D Layer w/ 4x Processing w/ 8x Processing Processing Layer Analysis Layer

  17. Conclusions • Emerging Technologies will play a significant new role • Risk is hard to avert right now • UCSB Computer Science and Engineering • Collaborate across disciplines to consider the entire SW/HW • Research that is driving industry • UCSB Technology in use in most Microprocessors and Networks • Always looking for more collaboration with industry partners

  18. http://www.cs.ucsb.edu/~arch/ NSF CNS 0524771, NSF CCF 0702798, NSF CCF 0448654

More Related