Decisions behind the design labview for compactrio sample projects
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Decisions Behind the Design: LabVIEW for CompactRIO Sample Projects. Meghan Kerry Embedded Software Product Manager Certified LabVIEW Developer (CLD). Agenda. Keys to quality in a software architecture Software architecture overview I/O safe states Watchdog timers Message communication

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Decisions Behind the Design: LabVIEW for CompactRIO Sample Projects

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Decisions behind the design labview for compactrio sample projects

Decisions Behind the Design: LabVIEW for CompactRIO Sample Projects

Meghan Kerry

Embedded Software Product Manager

Certified LabVIEW Developer (CLD)


Agenda

Agenda

  • Keys to quality in a software architecture

  • Software architecture overview

  • I/O safe states

  • Watchdog timers

  • Message communication

  • Error handling

  • System monitoring


Keys to quality in a software architecture

Keys to Quality in a Software Architecture

  • Define software architecture and identify architecture components

  • Create an architectural diagram

  • Consider key components such as data communication, error handling, etc.

  • Learn the foundational design patterns

  • Create new design patterns as required by your application (requires experience)


Data communication diagram

Data Communication Diagram

  • Documents foundational components:

    • Processes (loops)

    • Data communication paths

    • Type of data transfer


Data communication types

Data Communication Types


Typical compactrio system diagram

Typical CompactRIO System Diagram


Labview for compactrio sample projects

LabVIEW for CompactRIO Sample Projects

  • Pre-built architectures for embedded control and monitoring applications

  • Designed to ensure quality and scalability of a system


Basic fpga diagram

Basic FPGA Diagram

Performs deterministic and/or high speed control


State machine for hardware i o and control

State Machine for Hardware I/O and Control


Failure conditions that initiate safe states

Failure Conditions that Initiate Safe States

  • Examples (from Fail Safe Reference Design):

    • RT Safe – indicates the RT system is ready

    • Emergency Safe – tied to an emergency shut-off switch

    • Watchdog Safe – monitors the Real-Time system

    • Control Inputs Valid – monitors the inputs to the control algorithm

  • Based on system requirements


Basic fpga diagram1

Basic FPGA Diagram

Detects software failures

Recovers from software failures


Watchdogs

Watchdogs

  • A watchdog timer is a hardware counter that interfaces with the embedded software application to detect and recover from software failures

  • A user can then:

    • Reboot real-time target automatically

    • Perform user-defined recovery actions

  • Two types of watchdogs with NI Real-Time hardware:

    • LabVIEW Real-Time Watchdog

    • Real-Time <-> FPGA Watchdog (FPGA Fail Safe Design)


Labview real time only watchdog

LabVIEW Real-Time Only Watchdog

  • Uses hardware timer built into CompactRIO hardware

  • “Reset = True” reboots system if the watchdog process is starved


Labview real time watchdog

LabVIEW Real-Time Watchdog

  • Enable occurrence in expiration actions

  • Configure appropriate watchdog timeout and Watchdog Whack loop period


Real time fpga watchdog

Real-Time <-> FPGA Watchdog

Reset timer

Put control loop into a safe state, and reset system


Real time fpga watchdog1

Real-Time <-> FPGA Watchdog

  • Pet the watchdog at a user-defined watchdog pet rate

  • This resets the counter implemented in the FPGA VI

See Fail-Safe Control Reference Design whitepaper


Basic fpga diagram summary

Basic FPGA Diagram - Summary

Detects software failures

Recovers from software failures

Performs deterministic and/or high speed control


Basic real time processor diagram

Basic Real-Time Processor Diagram

Communicates messages with client

Sends messages to other processes or targets

Periodically communicates tags


Constructing a message

Constructing a Message

Examples

Data

Variant allows data-type to vary. Different messages may require different data

Command

String constant allows user to specify message


Queued message handler api

Queued Message Handler API


Queued message handler framework

Queued Message Handler Framework

Command Parser

Queued Message Handler Setup

Message handling loop

Watchdog Loop

Monitoring Loop


Queued message handler framework1

Queued Message Handler Framework

One or more messages handled per case

Command Parser

Communicate messages between processes or targets

Watchdog Loop

Monitoring Loop


Basic real time processor diagram1

Basic Real-Time Processor Diagram

Handles all error messages from FPGA and RT target


Error messages

Error Messages

  • Specific Error Handling

    • Code called in specific locations to respond with an action to specific error codes

    • Possible actions are retry, ignore, correct

  • Central Error Handling

    • High-level code that checks for errors in an entire system

    • Responds to classes of errors rather than specific codes

    • Uses the classification to determine which actions to take

Queue

Central Handler


Central error handling framework

Central Error Handling Framework

Command Receiver Loop

Specific Handler

UI message handling loop

Watchdog Loop

Specific Handler

Monitoring Loop

Specific Handler


Central error handling framework1

Central Error Handling Framework

Command Receiver Loop

Specific Handler

Watchdog Loop

Specific Handler

Monitoring Loop

Specific Handler


Central error handling framework2

Central Error Handling Framework

Return classification of error

Handle classified errors (update FPGA state and/or reboot system)

Get next error based on priority

Log and send all errors to UI


Basic real time processor diagram2

Basic Real-Time Processor Diagram

Communicates messages with client


Sending commands across the network

Sending Commands Across the Network

  • Network Streams are great for commands because are they are lossless

  • Tips:

    • Use Flush with zero timeout to minimize latency

    • Add code to handle UI disconnections (see Sample Project)


System monitoring

System Monitoring

Embedded processors have limited….

Disk Space

RAM

CPU Bandwidth

LostData

Crash

Starvation

EFFECT


System monitoring1

System Monitoring

Current value data can be sent to UI with Shared Variables

Monitor CPU usage per core

Execute loop periodically


Network published shared variables

Network Published Shared Variables

  • When to use the Static API:

    • Small number of variables (less than a dozen)

  • When to use the Programmatic API:

    • Iterate through a large number of variables

    • Dynamically change the IP address of the cRIO from the client (client side only)


Basic real time processor diagram3

Basic Real-Time Processor Diagram

Communicates messages with client

Sends messages to other processes or targets

Periodically communicates tags


Basic hmi diagram

Basic HMI Diagram

Processes UI Events and communicates messages with real-time system

Generates UI Events using the Event Structure

Periodically updates UI


Common variant architectures

Common Variant Architectures

  • Other LabVIEW for CompactRIO Sample Projects

    • LabVIEW FPGA Control

    • LabVIEW FPGA Control with Real-Time Sequencer Engine

    • LabVIEW Real-Time Control (RIO Scan Interface)

    • LabVIEW FPGA Waveform Acquisition and Logging

    • LabVIEW Data Logging and Supervisory Control


Fpga control with sequencer sample project

FPGA Control with Sequencer Sample Project


Real time control sample project

Real-Time Control Sample Project


Fpga waveform acquisition and logging

FPGA Waveform Acquisition and Logging


Demo labview fpga control sample project

Demo – LabVIEW FPGA Control Sample Project


Labview for compactrio sample projects1

LabVIEW for CompactRIO Sample Projects

  • Available in LabVIEW 2012 and later

  • Find more best practices at ni.com/compactriodevguide


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