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Advanced porting the framework

Advanced Porting The Framework

Intel Corporation

Software and Services Group


Agenda

Agenda

  • Create a New Platform Build

  • Minimal porting job to run EFI Shell

  • Platform specific porting features


Create a new project directory

New Platform Build

Create a New Project Directory

  • Identify the Platform that this Project is a part of, PROJECT_PLATFORM. Platforms are usually closely tied to a processor/north bridge/south bridge combination.

  • Choose a Project name, PROJECT_NAME. This is often defined in the PlatformTools.env. Currently we are describing Bearlake as an example project name.

  • Choose a Project family, PROJECT_FAMILY. This is often defined in the PlatformTools.env.

  • The Platform\PROJECT_FAMILY\

  • PROJECT_PLATFORM directory to Platform\PROJECT_FAMILY \PROJECT_NAME. In the case of the Bearlakeexample platform, the source directory to copy is Platform\IntelDpg\PROJECT_PLATFORM.


The framework directory tree 8 x code base

The Framework Directory Tree8.x code base

  • Framework

    • Application

    • Bus

    • Chipset

      • Lakeport - MemoryInit

      • Blackford - MemoryInit

      • ESB2

      • IntelIch - ICHX - SmBus

      • SMC

    • CPU

    • CSM

    • GUID

    • Include

    • Library

    • Platform

      • IntelDpg – LakeportPei – Dxe - Platform

      • IntelEsg – StarLakePei – Dxe - Platform

      • IntelSSG

        • Lakeport- Build

    • Ppi

    • Protocol

    • Tools

Bearlake

ICHX

Bearlake

Bearlake


Agenda1

Agenda

  • Create a New Platform Build

  • Minimal porting job to run EFI Shell

  • Platform specific porting features

  • \$(PLATFORM_SOUTH_PATH) for LAKEPORT is \IntelDpg\Lakeport


General overview

PWR ON

SEC

PEI

DXE

BDS

OS

General Overview

SECurity

Pre-Efi Initialization

Driver Xecution Environment

Boot Device Selection


Boot flow

Device, Bus, or Service Driver

Power on

[ . . Platform initialization . . ]

[ . . . . OS boot . . . . ]

Shutdown

Boot Flow

Exposed

PlatformInterface

Pre Verifier

OS-AbsentApp

CPUInit

Transient OS Environment

verify

Chipset Init

Board Init

Transient OS Boot Loader

OS-PresentApp

EFI Driver Dispatcher

Boot Manager

Intrinsic Services

?

Final OS Environment

Final OS Boot Loader

security

Security (SEC)

Pre EFI

Initialization (PEI)

Driver Execution Environment (DXE)

Boot Dev

Select(BDS)

Transient System Load

(TSL)

Run Time

(RT)

After Life

(AL)


System block diagram

legacy Option ROMs

legacy OS

Loader

legacy Option ROMs

legacy OS

Loader

EFI OS Loader

EFI OS Loader

EFI

EFI

Platform

Drivers

EFI

Drivers

Framework Drivers

Platform

Drivers

EFI

Drivers

Compatibility Support Module

Compatibility Support Module

Driver Execution Environment

Pre-EFI Initiialization (PEI)

Pre-EFI Modules

Architectural Protocols

Hardware Specific

Foundations

DXE Foundation

PEI Foundation

Hardware

Hardware

System Block Diagram


The framework directory tree 8 x code base1

The Framework Directory Tree8.x code base

  • Framework

    • Application

    • Bus

    • Chipset

      • BearLake - MemoryInit

      • Blackford - MemoryInit

      • ESB2

      • IntelIch - ICHX - SmBus

      • SMC

    • CPU

    • CSM

    • GUID

    • Include

    • Library

    • Platform

      • IntelDpg – BearlakePei – Dxe - Platform

      • IntelEsg – StarLakePei – Dxe - Platform

      • IntelSSG

        • Bearlake- Build

        • StarLake- Build

    • Ppi

    • Protocol

    • Tools


Porting sec

Minimal porting job to run EFI Shell

Porting SEC

  • Reset Fetches Code from FLASH

    • Enables Flat Protected Mode Execution

  • SEC Enables Temp Memory

    • Data and Stack Cached

    • Enables Execution of C Code

    • Transfers Control to PEI Foundation


Temporary memory

Minimal porting job to run EFI Shell

0xFFFF_FFFF

System ROM (16 MB)

System FLASH (512 KB)

Framework Code

and Data Stored Here

0xFFF8_0000

SEC Maps Unused

Region as Temporary

Memory

0xFF00_0000

Temp Memory

0xFEF0_0000

Local APIC

0xFEE0_0000

0xFED0_0000

I/O APIC

0xFEC0_0000

0xZZZ0_0000

PCI Resources

0xYYY0_0000

Low Top Of Memory

System Memory

0x0000_0000

Temporary Memory


Sec phase

Minimal porting job to run EFI Shell

SEC phase

  • Currently SEC phase is where the Reset vector will start

  • \Platform\$(PLATFORM_SOUTH_PATH)\Common\Sec\Ia32\ResetVec.asm

  • \Platform\$(PLATFORM_SOUTH_PATH)\Common\Sec\Ia32\Flat32.asm


Pei phase

Minimal porting job to run EFI Shell

PEI Phase

  • The PEI phase’s purpose is to:

    • Determine the boot mode

    • Perform low-level initialization of the platform

    • Discover and initialization main memory

    • Invoke recovery if desired

    • Transfer control to DXE or S3 waking vector


Pei phase overall initialization

Minimal porting job to run EFI Shell

PEI Phase Overall Initialization

  • Two PEIMs contain the majority of the platform’s initialization code :

    Platform\$(SOUTH_PLATFORM_PATH)\Pei\Platform\Stage1

    Platform\$(SOUTH_PLATFORM_PATH)\Pei\Platform\Stage2

  • The Platform Stage1 PEIM module does the platform initialization according to platform policy or board layout. Stage1 focuses on ICH related platform initialization, such as ICH GPIO initialize, since GPIO usage and initialize value is according to board layout design.

  • The Platform Stage2 PEIM module does the platform initialization according to platform policy or board layout. Platform Stage2 focuses on MCH related platform initialization, such as onboard Graphics enable/disable.


Platform specifics in platform h

Minimal porting job to run EFI Shell

Platform Specifics in Platform.h

\Platform\$(PLATFORM_SOUTH_PATH)\Common\Pei\Platform\Platform.h

  • Memory DIMM SMBUS address

  • Firmware Hub GPIO base address and recovery jumper number

  • ICH ACPI base address, ICH GPIO base address, SIO base address, ICH RCBA base address

  • Early resource address such as AC97 audio memory mapped IO base address, ICH SMBUS base address, ICH IDE base address.

  • ICH GPIO mappings

  • PEI memory usage

  • ICH ACPI timer related settings such as resolution, address, and max value.


Advanced porting the framework

Minimal porting job to run EFI Shell

GPIO Initialization

  • PEIM for ICH GPIO initialization

  • Table - mIchGpioInitTable


Code example

Minimal porting job to run EFI Shell

Code Example

FILE: Platform\ \$(PLATFORM_SOUTH_PATH)\ Common\Pei\Platform\Stage1\IchInit.c

static const ICH_GPIO_DEV mIchGpioInitTable [] = {

// Register OFFSET,Value

// 0/1 - Native function/GPIO

GPIO_USE_SEL, GPIO_USE_SEL_VAL,

GPIO_USE_SEL2, GPIO_USE_SEL2_VAL,

// 0/1 - Output/Input

GPIO_IO_SEL, GPIO_IO_SEL_VAL,

GPIO_IO_SEL2, GPIO_IO_SEL2_VAL,

// 0/1 - Active High/Low

GPIO_INV, GPIO_INV_VAL

};


Gpio values

Minimal porting job to run EFI Shell

GPIO Values

The table allows you to define the register offset and value that is needed to program the GPIO’s. You can set them up for input/output/tri-state and set the high/low values using the following defines:

GPIO_USE_SEL – which GPIO’s to program

GPIO_IO_SEL – which direction

GPIO_INV – switch High/Low state(setting)

These values – GPIO_USE_SEL, GPIO_IO_SEL, and GPIO_INV are defined in the file:

\Platform\$(PLATFORM_SOUTH_PATH)\Common\Pei\Platform\Platform.h


Ich initialization

Minimal porting job to run EFI Shell

ICH Initialization

  • Power-on ICH initialization is performed in PEI to:

    • Initialize the system buses (LPC, PCI, SMBUS)

    • Turn-off the watchdog timer

    • Program the interrupt pins

    • Other miscellaneous chipset initialization needed prior to memory detection

  • This initialization is performed in the file:

    Platform\ $(PLATFORM_SOUTH_PATH)\Pei\Platform\Stage1\IchInit.c

  • ICH address constants and additional ICH constants are declared in the file:

    Platform\ $(PLATFORM_SOUTH_PATH)\Pei\Platform\Platform.h

  • Platform component initialization based on user setup preferences is performed later in the DXE ICH initialization.

  • Resetting of the ICH is performed in the file:

    Chipset\IntelIch\IchX\IchInit\Pei\IchReset.c


Super i o initialization

Minimal porting job to run EFI Shell

Super I/O Initialization

  • Power-on Super I/O initialization is performed in the file:

    • Platform\($(PLATFORM_SOURCE_PATH)\Pei\Platform\Stage1\SioInit.c

  • Devices connected to the LPC bus (e.g. fans, floppy) component initialization is performed later in the DXE Super I/O initialization


Pci routing

Minimal porting job to run EFI Shell

PCI Routing

  • PCI IRQ routing table is required by some legacy OSes

  • DXE driver that perform PCI devices routing

    • Platform\$(PLATFORM_SOUTH_PATH)\Common\Dxe\LegacyBios\platform.c

  • Table – PirqTableHead


Pirq table code

PIRQ Table Code

Example in File:

Platform\$(PLATFORM_SOUTH_PATH)\Common\Dxe

\LegacyBios\platform.c

EFI_LEGACY_PIRQ_TABLE PirqTableHead = {

{0x52495024,00,01,0000,00,00,0000,0x8086,

0x122e,00000000,00,00,00,00,00,00,00,

00,00,00,00,00},

{

// Memory Controller devices

//

DEFINE_PCI_ROUTINE (0, 1, PIRQA, PIRQB, PIRQC, PIRQD, 0, 0), // PEG graphics port

DEFINE_PCI_ROUTINE (1, 0, PIRQA, PIRQB, PIRQC, PIRQD, 0x7, 0xFF), // PEG slot

DEFINE_PCI_ROUTINE (0, 2, PIRQA, 0, 0, 0, 0, 0), // On-board graphics

DEFINE_PCI_ROUTINE (0, 3, PIRQA, PIRQB, PIRQC, 0, 0, 0), // HECI

. . .


Pci irq routing in the acpi tables

PCI IRQ routing in the ACPI Tables

Example in File:

Platform\$(PLATFORM_SOUTH_PATH)\Common\Dxe\AcpiTables\asl\OnBoardPrt.asi

It contains the internal PCI devices and onboard PCI devices IRQ routing information. Generally, all internal PCI devices with ICH or MCH should be listed. For example, USB, IDE, SATA and AC97 controllers in ICH and graphics controller in MCH


Flash rom

Minimal porting job to run EFI Shell

Flash ROM

  • Implement EFI_FIRMWARE_VOLUME_ BLOCK_PROTOCOL

  • Enables Variable Write Services

  • Initializes platform specific flash device

    • Platform\Generic\RuntimeDxe\FvbServices\<Platform>

    • FWBlockService.c

  • Possible functions for FWH or SPI access

    • EnableFvbWrites ( )

    • EnablePlatformFvb ( )

    • PlatformGetFvbWriteBase ( )

    • SetPlatformFvbLock ( )


Smbus

Minimal porting job to run EFI Shell

SM Bus

SMBus

  • PEIM for ICH SMBus initialize

    • Chipset\IntelIch\IchX\Smbus IchSmbus.c

  • Functions to provide a standard way to access SMBus

    • SmbusExecute ( )

    • SmbusIoRead ( )

    • SmbusIoWrite ( )


Dxe ipl

Minimal porting job to run EFI Shell

DXE IPL

  • Shadow DXE IPL in permanent memory

    • To allow sharing of decompression algorithm with DXE

  • Allocate 128KB stack for DXE

  • Create HOBs

    • Decompression protocol passed as HOB

  • Firmware Volumes

    • Passed in HOB

  • Handle S3 transition

  • Switch Stacks to call DXE Main


Initialize system memory

Minimal porting job to run EFI Shell

SM Bus

Initialize System Memory

  • PEIM that performs system memory initialization

    • Chipset\<Chipset>

  • Memory detection

    • PEI_DUAL_CHANNEL_DDR_MEMORY_CONTROLLER_PPI

      • Reset

      • RowInfo

      • GetMemoryMap

      • DetectMemory

      • ConfigureMemory

  • Memory clock control

    • PEI_DUAL_CHANNEL_DDR_CLOCK_GENERATOR_PPI

      • Capabilities

      • GetFrequency

      • SetFrequency


Integrating memory init code

Minimal porting job to run EFI Shell

Integrating Memory Init Code

  • MRC directory Chipset\<Chipset>\MemoryInit

  • The file MemoryInit.Inf describes the Memory Reference code contained within its description (.dsc) file.

  • After calling the entry to this memory init routine and successfully exiting, the memory should be ready to use. It builds HOBs to describe the memory address space and their attributes.

  • Some of the HOB information that is produced by the MRC:

  • S3 Memory

  • SMRAM Descriptor HOB

  • Memory Descriptor HOB

  • T-size configuration setup option (variable)


Pei modules

Minimal porting job to run EFI Shell

SM Bus

PEI Modules

CPU PEIM

Platform

Init and CPU I/O

DXE IPL PEIM

Generic

Starts DXE Foundation

PCI Configuration PEIM

PCAT

Uses I/O 0xCF8, 0xCFC

Stall PEIM

PCAT

Uses 8254 Timer

Status Code PEIM

Platform

Debug Messages

SMBus PEIM

South Bridge

SMBus Transactions

Memory Controller PEIMs

North Bridge

Read SPD, Init Memory

Motherboard PEIM

Platform

FLASH Map, Boot Policy


Advanced porting the framework

Minimal porting job to run EFI Shell

PPI Example

typedef

EFI_STATUS

(EFIAPI *PEI_SMBUS_PPI_EXECUTE_OPERATION) (

IN EFI_PEI_SERVICE **PeiServices,

IN struct EFI_PEI_SMBUS_PPI *This,

IN EFI_SMBUS_DEVICE_ADDRESS SlaveAddress,

IN EFI_SMBUS_DEVICE_COMMAND Command,

IN EFI_SMBUS_OPERATION Operation,

IN BOOLEAN PecCheck,

IN OUT UINTN *Length,

IN OUT VOID *Buffer

);

typedef struct {

PEI_SMBUS_PPI_EXECUTE_OPERATION Execute;

PEI_SMBUS_PPI_ARP_DEVICE ArpDevice;

} EFI_PEI_SMBUS_PPI;


Advanced porting the framework

Minimal porting job to run EFI Shell

PEIM Pseudo Code

#define SMBUS_R_HD0 0xEFA5

#define SMBUS_R_HBD 0xEFA7

EFI_PEI_SERVICES *PeiServices;

SMBUS_PRIVATE_DATA *Private;UINT8 Index, BlockCount *Length;

UINT8 *Buffer;

BlockCount = Private->CpuIo.IoRead8 (

*PeiServices,Private->CpuIo,SMBUS_R_HD0);

if (*Length < BlockCount) {

return EFI_BUFFER_TOO_SMALL;

} else {

for (Index = 0; Index < BlockCount; Index++) {

Buffer[Index] = Private->CpuIo.IoRead8 (

*PeiServices,Private->CpuIo,SMBUS_R_HBD);

}

}


What are architectural protocols

Minimal porting job to run EFI Shell

What Are Architectural Protocols

  • Typically functions that isolate platform specific hardware (e.g. real-time clock)

  • Provide support for boot services and runtime services

  • Low level protocols that support DXE APIs (e.g. Boot and Runtime services)

  • Directly called by DXE core


Dxe architectural protocols

Minimal porting job to run EFI Shell

DXE Architectural Protocols

Watchdog

Generic

Uses Timer-based Events

Monotonic Counter

Generic

Uses Variable Services

Runtime

Generic

Platform Independent

CPU

Platform

Processor DXE Driver

BDS

Platform

Platform Policy and TSL phase

Timer

PCAT

Uses 8254 Timer

Metronome

PCAT

Uses 8254 Timer

Reset

PCAT

I/O 0xCF9

Real Time Clock

PCAT

I/O 0x70-0x71

Security

Platform

Platform Specific Authentication

Status Code

Platform

Debug Messages

Variable

Platform

Depends on FLASH Map


Dxe drivers consuming architectural protocols

Minimal porting job to run EFI Shell

DXE Drivers Consuming Architectural Protocols

  • Host bridge driver

    • Chipset\PcatCompatible\SimplePciHostBridge\Dxe

  • ICH initialize driver

    • Chipset\IntelIch\IchX\IchxInit\Dxe

  • IDE controller driver

    • Chipset\IntelIch\IchX\IdeController\Dxe

  • SMBus DXE driver

    • Chipset\IntelIch\IchX\Smbus\Dxe

  • Super I/O

    • Chipset\<SuperIO Vendor>\Dxe


Nt emulation timer arch protocol

Minimal porting job to run EFI Shell

NT Emulation Timer Arch Protocol

EFI_STATUS

TimerDriverSetTimerPeriod (

IN EFI_TIMER_ARCH_PROTOCOL *This,

IN UINT64 TimerPeriod

)

{

. . .

gWinNt->EnterCriticalSection (&mNtCriticalSection);

mTimerPeriod = TimerPeriod;

mCancelTimerThread = FALSE;

gWinNt->LeaveCriticalSection (&mNtCriticalSection);

mNtLastTick = gWinNt->GetTickCount ();

mNtTimerThreadHandle = gWinNt->CreateThread (

NULL,

0,

NtTimerThread,

&mTimer,

0,

&NtThreadId);

. . .

}


Itanium timer arch protocol

Minimal porting job to run EFI Shell

Itanium Timer Arch Protocol

EFI_STATUS

TimerDriverSetTimerPeriod (

IN EFI_TIMER_ARCH_PROTOCOL *This,

IN UINT64 TimerPeriod

)

{

. . .

mTimerCount = (mCpuFrequency * TimerPeriod) / NUMBER_OF_100NS_IN_A_SECOND;

SetupItm (mTimerCount);

// mov loc2 = ar.itc;;

// add loc2 = loc2, in0;;

// mov cr.itm = loc2

// srlz.d;;

ItcInterruptControl (TRUE, TIMER_VECTOR_NUMBER);

// mov loc2 = in1

// mov loc3 = 0x1

// mov loc4 = pr

// cmp.eq p6,p7 = in0,r0;;

//

// (p7) dep loc2 = r0,loc2,16,1;; // Clear mask to enable intr

// (p6) dep loc2 = loc3,loc2,16,1;; // Set mask to disable intr

//

// mov cr.itv = loc2;;

// srlz.d;;

// mov pr = loc4,0x1ffff

. . .

}


Xscale timer arch protocol

Minimal porting job to run EFI Shell

XScale Timer Arch Protocol

EFI_STATUS

TimerDriverSetTimerPeriod (

IN EFI_TIMER_ARCH_PROTOCOL *This,

IN UINT64 TimerPeriod

)

{

UINT64 Count;

UINT32 Data;

. . .

Count = DivU64x32 (MultU64x32 (TimerPeriod, OST_CRYSTAL_FREQ) + 5000000,

10000000, NULL);

mCpuIo->Mem.Read (mCpuIo,EfiWidthUint32,OSCR_BASE_PHYSICAL,1,&Data);

Data += (UINT32)Count;

mCpuIo->Mem.Write (mCpuIo,EfiWidthUint32,OSMR0_BASE_PHYSICAL,1,&Data);

mCpuIo->Mem.Read (mCpuIo,EfiWidthUint32,OIER_BASE_PHYSICAL,1,&Data);

Data |= (UINT32)1;

mCpuIo->Mem.Write (mCpuIo,EfiWidthUint32,OIER_BASE_PHYSICAL,1,&Data);

mCpuIo->Mem.Read (mCpuIo,EfiWidthUint32,ICMR_PHYSICAL,1,&Data);

Data |= (UINT32)(1 << SA_OST0_IRQ_No);

mCpuIo->Mem.Write (mCpuIo,EfiWidthUint32,ICMR_PHYSICAL,1,&Data);

. . .

}


8254 based timer arch protocol

Minimal porting job to run EFI Shell

8254 Based Timer Arch Protocol

EFI_STATUS

TimerDriverSetTimerPeriod (

IN EFI_TIMER_ARCH_PROTOCOL *This,

IN UINT64 TimerPeriod

)

{

UINT64 Count;

UINT8 Data;

. . .

Count = DivU64x32 (MultU64x32(119318, (UINTN) TimerPeriod) + 500000,

1000000, NULL);

Data = 0x36;

mCpuIo->Io.Write(mCpuIo,EfiCpuIoWidthUint8,TIMER_CONTROL_PORT, 1, &Data);

mCpuIo->Io.Write(mCpuIo,EfiCpuIoWidthFifoUint8,TIMER0_COUNT_PORT,2,&Count);

mLegacy8259->EnableIrq (mLegacy8259, Efi8259Irq0, FALSE);

. . .

}

Different Implementations

Same Protocol Interface


Serial terminal console services

Minimal porting job to run EFI Shell

Serial Terminal Console Services

BDS / EFI Shell

Virtual

Console

Simple Input

Protocol

Simple Text

Output Protocol

Physical

Console

Simple Input

Protocol

Simple Text

Output Protocol

Serial I/O Protocol

ISA I/O Protocol

Super I/O

PCI I/O Protocol

PCI Root Bridge

I/O Protocol

PCI Host Bridge Resource

Allocation Protocol

ISA ACPI Protocol


Serial terminal console drivers

Minimal porting job to run EFI Shell

Serial Terminal Console Drivers

BDS / EFI Shell

Generic

Console Splitter

Generic

Generic

Terminal

ISA Serial

PCAT

ISA Bus

Generic

Super I/O

PCI Bus

Generic

Platform Specific Policy

Console Platform

Platform

Work with Chipset Vendor

PCI Root Bridge

North Bridge

Work with Chipset Vendor

PCI Host Bridge

North Bridge

ISA ACPI

Super I/O

Work with Super I/O Vendor


Dxe driver for console services

Minimal porting job to run EFI Shell

DXE Driver for Console Services

  • Console Splitter Driver

    • Edk\Sample\Universal\Console\ConSplitter\Dxe

  • Graphics Console Driver

    • Edk\Sample\Universal\Console\GraphicsConsole\Dxe

  • Terminal Driver

    • Edk\Sample\Universal\Console\Terminal\Dxe

  • UGA Driver (optional)

    • Chipset\<Vendor>\Uga\Dxe


Porting summary do minimum to run efi shell

Minimal porting job to run EFI Shell

Porting SummaryDo Minimum to Run EFI Shell

Status Code

PEI

Platform

Memory Controller

PEI

North Bridge

SMBUS

PEI

South Bridge

Motherboard

PEI

Platform

Security

DXE

Platform

SM Bus

Status Code

DXE

Platform

Variable

DXE

Platform

Console Platform

DXE

Platform

PCI Root Bridge

DXE

North Bridge

PCI Host Bridge

DXE

North Bridge

ISA ACPI

DXE

Super I/O


Further information

Further Information

  • Documents Directory on CD

    • Framework Mini PortingGuide

    • FrameworkTechPortingRef

    • FrameworkPortingList


Advanced porting the framework

Q & A


Back up

Back up

Back Up


2009 release centrino mobile technology platform

2009 release Centrino Mobile Technology platform

  • Porting example

  • New form footprint no longer North / South Bridge template

  • Core / Uncore part of the Processor

  • Platform Control Hub (PCH) integrated successor to MCH + ICH instead of South Bridge

  • Power management considerations on mobile

  • Silicon released as Separate UEFI reference modules

    • PCH Reference code

    • Core / Uncore CPU Reference code

    • ACPI

    • Power Management

    • Memory Reference code


Platform

Platform

  • Platform

    • IntelDpg – BearlakePei – Dxe - Platform

    • IntelEsg – StarLakePei – Dxe - Platform

    • IntelMpg – MobilePlatform

      • AcpiTables

        • Dsdt

        • SsdtPtid

        • VaAcpiTables

      • Build

      • Include

      • LegacyBiosPlatform

      • Library

      • PciPlatform

      • PlatformSetup

      • SmbiosMisc

ACPI Module Package


Platform control hub chipset

Platform Control Hub - Chipset

  • Chipset

    • IntelIch

    • IntelPch – Mobile Chipset (IbexPeak)

      • ActiveBios

      • Include

      • IoTrap

      • LegacyInterrup

      • Library

      • PchInit

      • PchSmiDispatcher

      • PciExpress

      • Ppi

      • Protocol

      • RaidRom

      • Reset

  • S3Support

  • SampleCOde

  • SataController

  • SerialGpio

  • SmartTimer

  • SmBus

  • SmmControl

  • Spi

  • Uhci

  • Veci


Core uncore iio elements

Core/Uncore IIO Elements-

  • CPU

    • UncoreCommon

      • AcpiTables

      • Guid

      • Include

      • LegacyRegion

      • Library

      • PciHostBridge

      • SmbiosMemory

      • SmmAccess

    • FieldUncore

      • Iio (Integrated I/O )

        • IioInit

        • IioInitLib

        • Include

        • Protocol


Power management

Power Management-

  • Platform

    • IntelDpg – BearlakePei – Dxe - Platform

    • IntelEsg – StarLakePei – Dxe - Platform

    • IntelMpg – MobilePlatform

      • . . .

      • Common

        • PowerManagement

          • AcpiTables

          • Guid

          • Include

          • Library

          • Protocol

          • Smm


Memory init

Memory Init

  • CPU

    • UncoreCommon

    • . . .

    • FieldUncore

      • Iio (Integrated I/O )

        • . . .

      • CsiMemoryInit

        • CSI

        • PPI

        • PEI

        • Memory


Others

Others

  • Microcode updates

  • CSM


Agenda2

Agenda

  • Create a New Platform Build

  • Minimal porting job to run EFI Shell

  • Platform specific porting features


Add platform features ide

Platform specific porting features

Add Platform Features - IDE

BDS / EFI Shell

File Sys Protocol

File Sys Protocol

Disk I/O Protocol

Disk I/O Protocol

SM Bus

Partition

Block I/O Protocol

Block I/O Protocol

Disk I/O Protocol

Disk I/O Protocol

Physical Disk

Block I/O Protocol

Block I/O Protocol

PCI I/O Protocol

PCI Root Bridge

I/O Protocol

PCI Host Bridge Resource

Allocation Protocol

IDE Controller Init


Add platform features ide1

Platform specific porting features

Add Platform Features - IDE

BDS / EFI Shell

Generic

FAT

Generic

Partition

Generic

Disk I/O

Generic

SM Bus

IDE Bus

PCAT

PCI Bus

Generic

PCI Root Bridge

North Bridge

PCI Host Bridge

North Bridge

IDE Controller Init

South Bridge

IDE Channel Attributes


Add platform features

Platform specific porting features

Add Platform Features

  • Integrated USB

    • Work with Chipset Vendor

    • USB Host Controller Protocol

  • Integrated Video

    • Work with Chipset Vendor

    • UGA Draw and UGA I/O Protocol

  • Integrated LAN

    • Work with Chipset Vendor

    • UNDI Driver

  • AGP and PCI Slots

    • Work with IHVs to Provide EFI Drivers


Compatibility support module

Platform specific porting features

Compatibility Support Module

  • Implement Platform and Chipset Specific Protocols

    • Legacy BIOS Platform

    • Legacy Region

    • Legacy Interrupt

  • Enables POST of Legacy Option ROMs

    • Video Controllers

    • Disk Controllers

    • Network Interface Controllers

  • Enables Legacy OS Boot

    • Linux, Windows XP, Windows 2000


Csm drivers

Platform specific porting features

CSM drivers

  • LegacyBios driver

    • Csm\LegacyBios\Dxe

  • BiosThunk drivers – BIOS drivers for Legacy OS boot

    • Csm\BiosThunk\VgaMiniPort\Dxe

    • Csm\BiosThunk\Keyboard\Dxe

    • Csm\BiosThunk\Snp16\Dxe

    • Csm\BiosThunk\BlockIo\Dxe


Csm drivers cont d

Platform specific porting features

CSM Drivers Cont’d

  • Legacy Interrupt (PIRQ registers)

    • Chipset\IntelIch\LegacyInterrupt\Dxe\LegacyInterrupt.c

  • Legacy Region (shadow regions)

    • Chipset\<Vendor>\LegacyRegion\Dxe\LegacyRegion.c

  • Legacy BIOS Platform

    • Platform\<Vendor>\<Platform>\Dxe\LegacyBiosPlatform\LegacyBiosPlatform.c

    • Functions to prepare different tables (Option ROM services, etc.)


Add smm support to dxe

Platform specific porting features

Add SMM support to DXE

  • Base Protocol

    • Responsible for Processor state (in SMM) initialization and allocates SMM Memory

    • Cpu\<Processor>Base\Smm\SmmBase.inf

  • Access Protocol

    • Controls the visibility of the SMRAM on the platform

    • Chipset\<Vendor>\SmmAccess\Dxe\SmmAccess.inf

  • Control Protocol

    • Initiate SMI/PMI activations

    • Chipset\IntelIch\IchX\SmmControl\Dxe\SmmControl.inf


Acpi support

Platform specific porting features

ACPI Support

  • Provides ACPI support for a platform

    • Builds FADT table from built AML tables

    • Allows platform customization (APIC, GV3, OEMID)

    • Updates EFI System Table with ACPI table pointers

  • Composed of two drivers:

    • ACPI Support Driver (generic)

    • ACPI Platform Driver (platform specific)

  • Platform Driver runs during DXE phase (before BDS)

  • ScriptSave driver

    • DXE drivers call ScriptSave protocol to save the chipset and CPU configuration at normal boot path

    • The boot script engine in PEIM restores the chipset and CPU configuration done in previous DXE in S3 resume boot path

    • Universal\Acpi\BootScriptSave\Dxe\ScriptSave.inf


Add acpi support to dxe

Platform specific porting features

Add ACPI support to DXE

  • ACPI tables

    • Platform\<Vendor>\Dxe\AcpiTables

  • ASL code

    • Platform\<Vendor>\Dxe\AcpiTables\Asl\*.asi

  • Update Platform Driver for platform specifics

    • Platform\<Vendor>\<Platform>\Dxe\AcpiPlatform\AcpiPlatform.c


Efi s3 path

Platform specific porting features

SEC

PEI

DXE

BDS

Normal Boot

OS Boot

Save

Non-volatile

Storage (NVS)

Resume Script

Table in ACPI

NVS

Retrieve

Execute

SEC

S3 aware PEIMs restore PEI Phase configuration

Boot Script PEIM restores DXE phase configuration

S3 Resume

S3 Waking Vector

EFI S3 path


Add s3 support to dxe

Platform specific porting features

Add S3 Support to DXE

  • Architectural Protocol

    • Universal\Acpi\AcpiS3Save\Dxe

    • Universal\Acpi\S3Resume\Pei

  • Platform dependent Protocol

    • Platform\<Vendor>\Smm\IchS3Save


Bds driver

Platform specific porting features

BDS Driver

  • BDS driver

    • Edk\Sample\Platform\Generic\Dxe\PlatformBds

  • Connecting Consoles/Changing Platform Policy

    • Platform\<Vendor>\<Platform>\PlatformBds\Dxe\BdsPlatform.c

  • Language

    • Platform\Generic\Dxe\Bds\*.uni

  • Memory Test

Framework Designed to be Ported


Summary

Summary

  • Minimal porting effort for running EFI Shell.

  • Incrementally add platform specific features.

  • Modularity of drivers allows easy integration.

  • Legacy BIOS experience is still useful with the Framework.

  • Framework knowledge easily transfers to other architectures.


Further information1

Further Information

  • Documents Directory on CD

    • Framework Mini PortingGuide

    • FrameworkTechPortingRef

    • FrameworkPortingList


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