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Interface Design Compute Memory Timing. Omid Fatemi ([email protected]). Outline. Connecting to micro-processor Timing of microprocessor Timing of memory Interfacing memory. Compute. Convey. Cooperate. Typical Interface Design. Connect. Sense Reality Touch Reality Connect Transform.

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Interface design compute memory timing

Interface DesignComputeMemory Timing

Omid Fatemi

([email protected])


Outline
Outline

  • Connecting to micro-processor

  • Timing of microprocessor

  • Timing of memory

  • Interfacing memory


Typical interface design

Compute

Convey

Cooperate

Typical Interface Design

Connect

Sense Reality

Touch Reality

Connect

Transform

Embedded Systems

Micros

Assembler, C

Real-Time

Memory

Peripherals

Timers

DMA

Busses

Protocols

Standards

PCI

IEEE488

SCSI

USB & FireWire

CAN

PC interfaces

HCI


Processor timing diagram for any memory read machine cycle
Processor Timing Diagramfor any memory read machine cycle


Processor timing diagram for any memory write machine cycle
Processor Timing Diagramfor any memory write machine cycle


When interfacing memory chips to a microprocessor consider the following
When interfacing memory chips to a microprocessor, consider the following:

  • TAVDV – address access time

  • TRLDV – read access time

  • TDVWH – memory setup time

  • TWHDX – data hold time

  • TWLWH – write pulse width

    Refer to 8088 data manual



Timing requirements during memory read
Timing Requirements during Memory Read the following:

  • TAVDV

    • 3TCLCL – TCLAV – TDVCL

    • Address Access Time

    • from Address is Valid to Data is Valid


Read access time trldv
Read Access Time (TRLDV) the following:


Timing requirements during memory read1
Timing Requirements during Memory Read the following:

  • TRLDV

    • 2TCLCL – TCLRL – TDVCL

    • Read Access Time

    • from Read Signal is Low to Data is Valid



Timing requirements during memory write
Timing Requirements during Memory Write the following:

  • TDVWH

    • 2TCLCL – TCLDV +TCVCTX

    • Memory Setup Time

    • from Data is Valid to Write Signal is High


Data hold time twhdx
Data Hold Time (TWHDX) the following:


Timing requirements during memory write1
Timing Requirements during Memory Write the following:

  • TWHDX

    • TCLCH – X

    • Data Hold Time (after WR’)

    • from Write Signal is High to Data is Invalid (Inactive)



Timing requirements during memory write2
Timing Requirements during Memory Write the following:

  • TWLWH

    • 2TCLCL – Y

    • Write Pulse Width / Write-Time

    • from Write Signal is Low to Write Signal is High



Computation of timing requirements for 8088 using a 4mhz clock
Computation of Timing Requirements for 8088 using a 4Mhz Clock

  • TAVDV

    • 3TCLCL – TCLAVmax – TDVCLmin

    • 3(250 ns) – 110 ns – 30 ns

    • 610 ns

  • TRLDV

    • 2TCLCL – TCLRLmax – TDVCLmin

    • 3(250 ns) – 165 ns – 30 ns

    • 555 ns



Computation of timing requirements for 8088 using a 4mhz clock1
Computation of Timing Requirements for 8088 using a 4Mhz Clock

  • TDVWH

    • 2TCLCL – TCLDVmax +TCVCTXmin

    • 2(250 ns) – 110 ns + 10 ns

    • 400 ns

  • TWHDX

    • TCLCH – X

    • 118 ns – 30 ns

    • 88 ns

  • TWLWH

    • 2TCLCL – Y

    • 2(250 ns) – 60 ns

    • 440 ns


Timing requirements for 8088 using a 4mhz clock
Timing Requirements for 8088 using a 4Mhz Clock Clock

  • TAVDV = 610 ns

  • TRLDV = 555 ns

  • TDVWH = 400 ns

  • TWHDX = 88 ns

  • TWLWH = 440 ns



Timing requirements for 6264 sram
Timing Requirements for 6264 SRAM clock?

  • TAVDV = ?

  • TRLDV = ?

  • TDVWH = ?

  • TWHDX = ?

  • TWLWH = ?


Hm6264b series read timing requirements

HM6264B clock?

-

8L

HM6264B

-

10L

Symbol

Parameter

Units

Min

Max

Min

Max

t

Read cycle time

85

100

ns

RC

t

Address access time

85

100

ns

AA

t

Chip select access time (CS1’)

85

100

ns

CO1

t

Chip select access time (CS2’)

85

100

ns

CO2

t

Output enable to output valid

45

50

ns

OE

Chip selection to output in low

-

Z

t

10

10

ns

LZ1

(CS1)

Chip selection to output in low

-

Z

t

10

10

ns

LZ2

(CS2)

t

Output enable to output in low

-

Z

5

5

ns

OLZ

Chip deselection in to output i

n

t

0

30

0

35

ns

HZ1

high

-

Z (CS1’)

t

HM6264B Series Read TIMING REQUIREMENTS

Chip deselection in to output in

0

30

0

35

ns

HZ2

high

-

Z (CS2’)

t

Output disable to output in high

-

Z

0

30

0

35

ns

OHZ

t

Output hold from address change

10

10

ns

OH





Timing requirements for 6264 sram1
Timing Requirements for 6264 SRAM clock?

  • TAVDV = tAA

  • TRLDV = tOE

  • TDVWH = tDW

  • TWHDX = tDH

  • TWLWH = tWP


Timing requirements for hm6264b 8l
Timing Requirements for HM6264B-8L clock?

  • TAVDV = tAA = ?

  • TRLDV = tOE = ?

  • TDVWH = tDW = ?

  • TWHDX = tDH = ?

  • TWLWH = tWP = ?




Timing requirements for hm6264b 8l1
Timing Requirements for HM6264B-8L clock?

  • TAVDV = tAA = 85 ns

  • TRLDV = tOE = 45 ns

  • TDVWH = tDW = 40 ns

  • TWHDX = tDH = 0 ns

  • TWLWH = tWP = 55 ns


Comparing timing requirements of 8088 using 4 mhz clock and hm6264b 8l
Comparing Timing Requirements of clock?8088 (using 4 Mhz clock) and HM6264B-8L



Timing requirements for 2764 eprom
Timing Requirements for 2764 EPROM clock?

  • TAVDV = ?

  • TRLDV = ?

  • TDVWH = ?

  • TWHDX = ?

  • TWLWH = ?




Timing requirements for 2764 eprom1
Timing Requirements for 2764 EPROM clock?

  • TAVDV = tAVQV

  • TRLDV = tGLQV

  • TDVWH = N/A

  • TWHDX = N/A

  • TWLWH = N/A


Timing requirements for 2764 eprom2
Timing Requirements for 2764 EPROM clock?

  • TAVDV = tAVQV = ?

  • TRLDV = tGLQV = ?

  • TDVWH = N/A

  • TWHDX = N/A

  • TWLWH = N/A



Timing requirements for m2764a 3
Timing Requirements for M2764A-3 clock?

  • TAVDV = tAVQV = 180 ns

  • TRLDV = tGLQV = 65 ns

  • TDVWH = N/A

  • TWHDX = N/A

  • TWLWH = N/A


Comparing timing requirements of 8088 using 4 mhz clock and m2764a 3
Comparing Timing Requirements of clock?8088 (using 4 Mhz clock) and M2764A-3



Comparing timing requirements of 8088 using 4 mhz clock and a certain slow memory chip
Comparing Timing Requirements of 8088?8088 (using 4 Mhz clock) and a certain “slow” memory chip


Recall write pulse width write time twlwh
Recall: 8088?Write Pulse Width / Write-Time (TWLWH)



Comparing timing requirements of 8088 using 4 mhz clock and a certain memory chip
Comparing Timing Requirements of 8088?8088 (using 4 Mhz clock) and a certain memory chip

caused by 1 wait state during a memory write on the “slow” memory chip


How do we produce a wait state
How do we produce a wait state? 8088?

  • By turning the READY input of the 8088 microprocessor to LOW




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