Yield Estimation based on Layout & Process Data. by Karthik Subramanian Master’s Thesis Work Mar 2003. Contents. Introduction to yield. Concept of “critical area” in ICs. Interconnect yield model. Yield estimation at the schematic stage. Yield estimation at the layout stage.
Master’s Thesis Work
Cchip = Cwf/(Nchip * Y)
(a). High wafer yield through contamination control has become difficult and hard to achieve.
(b). Increase in fabless design houses, which have little control over the manufacturing process; can control costs only by optimizing designs for higher yield.
(a).Functional yield loss (Yfnc) due to spot defects (shorts & opens).
(b).Parametric yield loss (Ypar) due to global process disturbances.
Total Yield = Yfnc * Ypar
(a). The use of the metal layer is more extensive than that of any other layer in the IC.
(b). The defect count is more in the metal layer.
A = die area; D = defect density.
ACr= critical area; r0 = defect radius; r1 = half (the min. Spacing between metals); K and p are model parameters.
(a). Additional Interconnect layers.
(b). Reducing Cell Utilization.
(c).Relaxing metal design rules.
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