1 / 12

Virgo Control Electronic upgrade Annecy/Pisa/EGO B.Mours

Virgo Control Electronic upgrade Annecy/Pisa/EGO B.Mours. Post C6 upgrades (I). Sensitivity from Aug 12 (End of C6) Sensitivity from Aug 27. Improvement due to Linear Alignment (4 loops closed instead of 2). 2kHz bump due to detection tower pump (exciting external bench resonances).

warren
Download Presentation

Virgo Control Electronic upgrade Annecy/Pisa/EGO B.Mours

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. Virgo Control Electronic upgrade Annecy/Pisa/EGO B.Mours ESF Workshop-Perugia

  2. Post C6 upgrades (I) Sensitivity from Aug 12 (End of C6) Sensitivity from Aug 27 Improvement due to Linear Alignment (4 loops closed instead of 2) 2kHz bump due to detection tower pump (exciting external bench resonances) New optical setup for B5  Reduction of laser frequency noise BS z control noise : alpha tuning PR z control noise reduction (Neo filter with roll-off @ 100 Hz) DAC noise reduction ESF Workshop-Perugia

  3. Current main Virgo control loop Timing ITF Control West End Input Mode-Cleaner ( L:150m) 3Km Fabry-Perot Cavity (F:50, L’:100Km) West Input IMC Control Recycling Beam Splitter Recycling Cavity (P:1Kw) Laser Nd:YAD P:20W, :1.064m Input Bench North Input North End Output Mode-Cleaner Detection OMC Control • Frequency: 10 kHz100µs • 30 VME crates for this loop • Main limitations: • Old hardware (~10 years old) • DSP and CPU performances • Time is shared between • Computing • Interrupt response • Data access (on VME bus : ~ 3-4 words/µs + 3 µs) • Input, Output, Monitoring • fitting complex filters or algorithms ? • Delay (distributed system): AR Filter+Pr+GC+Sc+Filter  500 µs • Impact on the loop bandwidth • Sampling rate of the dark port and monitoring channel (20kHz) • Fast readout could be useful for debugging • Analog servo for the frequency stabilization ESF Workshop-Perugia

  4. Redesign of the control Electronic • Increase • Computing performances: new DSP and CPU • Data throughput: new DOL • gain a factor 10: 100Mbits/s 1 Gbits/s) • Lower Noise: New ADC, DAC, differential connection (ADC, timing) • More channels: more compact electronic • New timing system • To be interfaced to the new boards • distribute the GPS signal: simpler • A possible goal for the main loop: 60 kHz • 1/60k=16us = Arm length • Will increase the DAQ rate • Now 18 MB/s (6-7 MB/s of compressed data) • Front end, preprocessing, data transport, storage ESF Workshop-Perugia

  5. New processing board • Replace 5 VME boards by 1: • 1 VME CPU: PC 104 or PC on PMC • 2 Digital Optical Link+1 Timing:  TOLM • 1 DSP board  DSP mezzanine • To be used by Pr, GC, Sa, Sc… • Payoff: Integrated DAQ (frame building) ESF Workshop-Perugia

  6. New DSP Mezzanine DSPV03AFunctional Blocks Diagram VME FastEthernet PCI2VMEBridge PCIBridge CPU Module Console PCI Link Port 4 PCI2LBBridge Dual Port Memory 2 DSP#1 DSP#3 2 DSP#5 DOL Timing Serial link DSP Local Bus 4 3 LB2VSBBridge FlashMemory DSP#2 DSP#4 DSP#6 Serial link 4 Front Panel VSB Link Port 1 DSP @ 60 MHz (60 MFLOPS peak)  6 DSP’s @ 100MHz (ADSP211160N SHARC DSP; 3.4 GFLOPS) ESF Workshop-Perugia

  7. MDSPAS – Top View Dual Port Memory M A 4 3 2 5 6 1 B DSP FPGA • A prototype exist since a few weeks ESF Workshop-Perugia

  8. TOLM • TOLM • Timing and Optical Link Mezzanine • Interfaces: • PCI interface for configuration and tests • TIMING part: • 1PPS and GPS on differentiel link (one single cable; RJ45) • Changed to IRIG-B on coax cable + fibers. • 1 Serial link to DSP for GPS time info • 2 front panel output for pulses • 2 DPS output for pulses • Digital Optical Link part • 2 input and output fibers • Monomode or multimodes • Higher data rate: 155Mbits/s  1GBits/s • 4 DSP links (PCI-J4) • Status: • Prototype available since last September • Developing the FPGA software and testing. ESF Workshop-Perugia

  9. Timing generation • The TOLM use always a local oscillator (TCXO) • The local oscillator will be lock on a GPS reference • Need: • Distribution of GPS clock + absolute timing information: IRIG-B • Selection of clock and distribution boards: • In progress IRIG-B IRIG-B GPS Antenna TOLM Fiber to coper IRIG-B Copper to Fiber CommercialGPS Clock 3.3 Km max. 3 m max Optic Fibers Coax cable ESF Workshop-Perugia

  10. Optical Link: Extension board TOLM Extension Board 1 1 1 Pr/ADC Pr/ADC TOLM TOLM 2 2 2 Link Port 3 Link Port Link Port Carte PC Carte PC Carte PC N N M Carte DSP ExtensionBoard 1 Carte DSP Carte DSP 2 Processing Board 3 Processing Board Processing Board Suspension 1 M Suspension 2 • Need Fan-out board in the case of • Global control connections • Multiple Pr/ADC input • Multiple inputs(8)/single output • Single input/ Multiple outputs • Need simple protocol to route the data • Development: started ESF Workshop-Perugia

  11. New ADC/DAC • New ADC: • More bits (18?) • Faster sampling rate (100 kHz – 1 MHz) • Input compression (whitening) filters • On board decompression option • Low noise: Optical link to processing boards • Include (part of) the TOLM design for timing generation? • Versatile enough to reduce the number of ADC type (Currently 3). • New DAC • Need of a very high dynamical range for actuators. • The DAC board used has -98 dB of total harmonic distortion + noise • while newer chips are available on market with –120 dB • Two different design approaches are under evaluation • Standard VME board, 16 ch. 24bits (nominal) • Distributed system • Status: • Early design phase (selecting the main components) ESF Workshop-Perugia

  12. Conclusion • Development of the new control system is in progress • It will be a MAJOR change for Virgo • Hardware and Software • Probably several weeks of down time in 2007 (?) ESF Workshop-Perugia

More Related