Critical Review of Critical Assessment Section

1. Critical Review ofCritical Assessment Section Ken Uchida Tokyo Institute of Technology

2. Contents • Quantitative Logic Assessment • Unity Gain Inverter • 2-input NAND Gate • 32-bit Shift Register • Speed, Aerial Footprint, Power Dissipation • Performance Projection for 15nm CMOS Tech. • Survey-Based Benchmarking • Tech. Highlighted for Accelerated Development

3. Normalized Performance of ERD Devices Figure ERD5 Median delay, energy, and area of proposed devices, normalized to ITRS 15-nm CMOS. (Based on principal investigators’ data; from Rev.

4. Energy-Delay Product Figure ERD6: Energy versus delay of a NAND2 gate in various post-CMOS technologies. Projections for both high-performance and low-power 15nm CMOS are included as reference. All values are a snapshot in time, and will change as work continues.

5. Beyond-CMOS Tech. Non-charge Token Figure ERD7: Inverter energy and delay and interconnect delay (*characteristic of transport over 10um) for various beyond-CMOS technologies. Projections for both high-performance and low-power 15nm CMOS included as reference. Solid dots indicate the switch is intrinsically non-volatile. All values are a snapshot in time, and will change as work continues.

6. Balance betweenSpeed, Area, Interconnect speed Figure ERD8: Transport impact on switch delay, size, and area of control. Circle size is logarithmically proportional to physically accessible area in one delay. Projections for 15nm CMOS included as reference.

7. Logical Effort Figure ERD9: Estimated logical effort – a measure of the relative “expense” required to perform a given logic function – for new switches in both simple combinatorial and complex circuits (lower values are preferred). Projections for 15nm CMOS included as reference.

8. Spider Chart

9. Change of “Technology” Names (1) 1) Ferroelectric Memory (2011) is compared with Ferroelectric FET Memory (2009) and Ferroelectric FET (2007 and 2005). Ferroelectric Memory(2011)->Ferroelectric FETand Ferroelectric Polarization ReRAM (Ferroelectric Memory should be “Ferroelectric FET Memory) 2) Redox Resistive Memory (2011) is compared with Nanoionic Memory (2009) and ionic (2007). 3) Mott Memory (2011) is compared with Electronic Effects Memory (2009) and Electronic Effects (2007). 4) CNT MOSFET (2011) is compared with CNT MOSFET (2009) and 1D structures (2007 and 2005).

10. Change of “Technology” Names (2) 5) GNR MOSFET (2011) is compared with GNR MOSFET (2009) and 1D structures (2007 and 2005). 6) NW MOSFET (2011) is compared with Nanowire MOSFETs (2009) and 1D structures (2007 and 2005). 7) Ge and InP n-Channel MOSFET (2011) is compared with Ge MOSFETs (2009) and Channel Replacement (2007). 8) GeInSb and GaSbP p-Channel MOSFET (2011) is compared with III-V Compound Semiconductor MOSFETs (2009) and Channel Replacement (2007).

11. Change of “Technology” Names (3) 9) Spin FET and Spin MOSFET (2011) is compared with Spin FETs (2009) and Spin Transistors (2007 and 2005). 10) Nano Magnetic Logic (2011) is compared with Nanomagnetic Devices (2009) and Ferromagnetic (2007 and 2005). 11) BisFET (2011) is compared with Psuedomorphic Devices (2009). 12) Ferroelectric Negative Cg Devices (2011) is compared with Negative Cg FETs (2009).