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ECE 645 Computer Arithmetic

Lecture Roadmap. Sequential MultipliersUnsignedSignedRadix-2 Booth RecodingHigh-Radix Multiplication PrinciplesRadix-4Radix-4 Booth RecodingHigh-Radix Sequential MultipliersUsing Carry-Save AddersSerial MultipliersModular Multiplication. Required Reading. B. Parhami, Computer Arithmetic: A

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ECE 645 Computer Arithmetic

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    1. Lecture 8: Sequential Multipliers ECE 645Computer Arithmetic 3/25/08

    2. Lecture Roadmap Sequential Multipliers Unsigned Signed Radix-2 Booth Recoding High-Radix Multiplication Principles Radix-4 Radix-4 Booth Recoding High-Radix Sequential Multipliers Using Carry-Save Adders Serial Multipliers Modular Multiplication

    3. Required Reading B. Parhami, Computer Arithmetic: Algorithms and Hardware Design Chapter 9, Tree and Array Multipliers Chapter 10, High-Radix Multipliers Chapter 12, Variations in Multipliers Note errata at: http://www.ece.ucsb.edu/~parhami/text_comp_arit.htm#errors

    4. Sequential Multipliers

    5. Multiplication Architectures

    6. Notation

    7. Multiplication of Two 4-bit Unsigned Binary Numbers in Dot Notation

    8. Basic Multiplication Equations

    9. Sequential Shift-and-Add Multipliers: Right-Shift Algorithm (Unsigned)

    10. Sequential Shift-and-Add Multipliers: Right-Shift Algorithm

    12. Area Optimization for the Sequential Shift-and-Add Multiplier with the Right-shift Algorithm

    13. Sequential Shift-and-Add Multipliers: Left-Shift Algorithm (Unsigned)

    14. Sequential Shift-and-Add Multipliers: Left-Shift Algorithm

    16. Sequential Shift-and-Add Multipliers: Right-Shift Algorithm for Multiply-Add

    17. Sequential Shift-and-Add Multipliers: Left-Shift Algorithm for Multiply-Add

    18. Signed Multiplication Previous sequential multipliers are for unsigned multiplication For signed multiplication: Right-shift sequential algorithms (shift-add) will work directly if 2's complement multiplier is POSITIVE Also assume sign-extended operation for p(i) + xia If 2's complement multiplier is NEGATIVE than must use "negative weight" representation and subtract xk-1a instead of add in last cycle Also assume sign-extended operation for p(i) + xia Slight increase in area due to control and one-bit sign extension on inputs of adder Unsigned: k bit number + k bit number ? k+1 bit number Signed: k+1 bit sign extended number + k+1 bit sign extended number ? k+1 bit number

    21. Sequential Signed Multiplication with Left-Shifts

    22. Sequential Shift-and-Add Multiplier with a Carry Save Adder

    23. Radix-2 Booth Recoding

    24. Radix-2 Booth Recoding Can be used to recode unsigned multipliers or signed (two's complement) multipliers Can reduce average number of additions required Not normally used in practice due to variable delay, but serves as help to understand radix-4 Booth recoding, which is used often in practice

    25. Radix-2 Booth Recoding

    26. Radix-2 Booth Recoding

    28. High-Radix Multipliers

    29. High-Radix Notation

    30. Radix-4, or Two-Bit-at-a-Time, Multiplication in Dot Notation

    31. Basic Multiplication Equations

    32. High-Radix Shift/Add Algorithms: Right-Shift High-Radix Algorithm

    33. High-Radix Shift/Add Algorithms: Left-Shift High-Radix Algorithm

    34. The multiple generation part of a radix-4 multiplier with precomputation of 3a

    35. Example of Radix-4 Multiplication using the 3a multiple (unsigned)

    36. The multiple generation part of a radix-4 multiplier

    37. Higher Radix Multiplication In radix-8, one must precompute 3a, 5a, 7a Overhead becomes prohibitive and does not help However, when we discuss CSA this may be useful

    38. Radix-4 Booth Recoding Typically used for two's complement multiplication, but can also use for unsigned multiplication Radix-4 Booth recoding also called "modified" Booth recoding Goal is to reduce the number of partial products (see next slide) Increase the complexity of "multiple-forming circuits" Formerly were AND gates in normal tree multiplication Reduces number of partial products by approximately half Formerly, k-bit two's multiplier implies k partial products Now k-bit two's complement multiplier recoded into ceil(k/2) digits, so ceil(k/2) partial products

    39. Full Tree Architecture

    40. Radix-2 and Radix-4 Booth Recoding

    42. Radix-4 Booth Recoding Examples: Unsigned xk-1=0 k=12 bits, xk-1 = 0 ? 6 digits Unsigned: (011010101010)2 = (1706)10 = 2 * 45 + -1 * 44 + -1 * 43 + -1 * 42 + -1 * 41 + -2 * 40

    43. Radix-4 Booth Recoding Examples: Unsigned xk-1=1 k=12 bits, xk-1 = 1 ? 7 digits Unsigned: (111010101010)2 = (3754)10 = 1 * 46 + -1 * 44 + -1 * 43 + -1 * 42 + -1 * 41 + -2 * 40

    44. Radix-4 Booth Recoding Examples: Signed xk-1=0 k=12 bits, xk-1 = 0 ? 6 digits Signed: (011010101010)2 = (1706)10 = 2 * 45 + -1 * 44 + -1 * 43 + -1 * 42 + -1 * 41 + -2 * 40

    45. Radix-4 Booth Recoding Examples: Signed xk-1=1 k=12 bits, xk-1 = 1 ? 6 digits Signed: (111010101010)2 = (-342)10 = -1 * 44 + -1 * 43 + -1 * 42 + -1 * 41 + -2 * 40

    46. Radix-4 Unsigned and Signed Summary Unsigned If xk-1 = 0, requires ceil(k/2) digits If xk-1 = 1, requires ceil((k+1)/2) digits Or you can always add a '0' to the MSB of both the multiplicand and multiplier, treat the multiplication as signed, then remove the two '0' MSBs of the output Signed Requires ceil(k/2) digits

    47. Radix-4 Booth Multiplication (Two's Complement): Sequential Right-Shift

    48. Booth Recoding and Multiple Selection Logic for High-Radix Multiplication (Sequential Multiplier)

    49. Full Tree Architecture

    50. Booth Recoding and Multiple Selection Logic for High-Radix Multiplication (Tree Adder)

    51. High-Radix Sequential Multipliers

    52. Multiplication Architectures

    53. Sequential Shift-and-Add Multiplier with a Carry Save Adder

    54. Radix-4 multiplication with a carry-save adder

    55. Radix-4 multiplication with a carry-save adder and Radix-4 Booth-recoding

    56. Radix-4 multiplier with two carry-save adders

    57. Radix-16 multiplier with carry-save adders

    58. Bit-Serial Multipliers

    59. Bit Serial Multipliers

    60. Systolic Array Systolic array: synchronous arrays of processing elements that are interconnected by only short, local wires thus allowing very high clock rates

    61. Semisystolic Bit-Serial Multiplier (1)

    62. Semisystolic Bit-Serial Multiplier (2)

    63. Retiming

    64. Retimed Semisystolic Bit-Serial Multiplier (1)

    65. Retimed Semisystolic Bit-Serial Multiplier (1)

    66. Systolic Bit-Serial Multiplier

    67. Modular Multiplication

    68. Modular Multiplication

    69. Modular Multiplication

    70. Modular Multiplication

    71. Modulo (2b-1) Carry Save Adder

    72. 4 x 4 Modulo 15 Multiplier

    73. 4 x 4 Modulo 13 Multiplier

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