Understanding Engineers #1

1. Understanding Engineers #1 • The graduate with a Science degree asks, "Why does it work?" • The graduate with an Engineering degree asks, "How does it work?" • The graduate with an Accounting degree asks, "How much will it cost?" • The graduate with an Arts degree asks, "Do you want fries with that?" CS 150 - Spring 2007 – Lec #18 – Mid #2 Review - 1

2. Understanding Engineers #2 • MS CS -- Soft-ware • MS EE -- Hard-ware • MBA -- Un-a-ware • MFA -- No-ware CS 150 - Spring 2007 – Lec #18 – Mid #2 Review - 2

3. Midterm II • THIS Thursday, 22 March (that is TWO days from today!), 2:10 -- 3:30+, CS 150 Lab • Lectures 10, 11, 12, (no lecture 13!), 14, 15, 16; Labs #4 and #5 (Debugging/Logic Analyzers) + Checkpoints #0 and #1 (SDRAM + Video Encoder) • Don’t forget: Spring 05/Fall 05 exams are on-line! • 5 x 10 point questions, mostly design-oriented • Closed book, open crib sheet; PENCIL, not pen! • Two review sessions: Tu 8 PM and W 8 PM in the lab • NOTE: Discussion sections and lab lecture cancelled this week CS 150 - Spring 2007 – Lec #18 – Mid #2 Review - 3

4. Sequential Logic Implementation • Models for representing sequential circuits • Mealy, Moore, and synchronous Mealy machines • Verilog specifications for state machines • Finite state machine design procedure • Deriving state diagram from word specifications • Deriving state transition table • Determining next state and output functions • Implementing combinational logic CS 150 - Spring 2007 – Lec #18 – Mid #2 Review - 4

5. SDRAM Memory Controller • Static RAM Technology • 6T Memory Cell • Memory Access Timing • Dynamic RAM Technology • 1T Memory Cell • Memory Access Timing • Theory in lecture, but practical detailed memory system organization and timing in Lab Checkpoint #0 CS 150 - Spring 2007 – Lec #18 – Mid #2 Review - 5

6. Two-way Video Conferencing Project • Project Concept and Background • SDRAM Controller (Checkpoint #0) • Video Encoder/Display System (Checkpoint #1) CS 150 - Spring 2007 – Lec #18 – Mid #2 Review - 6

7. Video Decoder Multiport SDRAM Memory System Video Encoder SDRAM (Checkpoint #0) Camera Display Videostream Video Decoder Multiport Arbitration Video Encoder (Checkpoint #1) Checkpoint #2 Wireless Transceiver (Checkpoint #3) Checkpoint #4 Videoconferencing System Concept CS 150 - Spring 2007 – Lec #18 – Mid #2 Review - 7

8. Computer Organization • Computer design as an application of digital logic design procedures • Computer = processing unit + memory system • Processing unit = control + datapath • Control = finite state machine • Inputs = machine instruction, datapath conditions • Outputs = register transfer control signals, ALU operation codes • Instruction interpretation = instruction fetch, decode, execute • Datapath = functional units + registers • Functional units = ALU, multipliers, dividers, etc. • Registers = program counter, shifters, storage registers CS 150 - Spring 2007 – Lec #18 – Mid #2 Review - 8

9. Register Transfer C  A Sel  0; Ld  1 C  B Sel  1; Ld  1 A B Sel0 D E C Sel 0 1 Sel1 Bus Clk Sel Ld Ld C Clk A on Bus B on Bus Ld C from Bus ? CS 150 - Spring 2007 – Lec #18 – Mid #2 Review - 9

10. MUX MUX MUX MUX rt rs rd R4 rd rs R4 rt R4 rs rt rd MUX BUS Register Transfer • Point-to-point connection • Dedicated wires • Muxes on inputs ofeach register • Common input from multiplexer • Load enablesfor each register • Control signalsfor multiplexer • Common bus with output enables • Output enables and loadenables for each register CS 150 - Spring 2007 – Lec #18 – Mid #2 Review - 10

11. State Machine Implementation • Alternative controller FSM implementation approaches based on: • Classical Moore and Mealy machines • Time state: Divide and Counter • Jump counters • Microprogramming (ROM) based approaches • branch sequencers • horizontal microcode • vertical microcode CS 150 - Spring 2007 – Lec #18 – Mid #2 Review - 11

12. Wait/ Wait/ Wait/ Time State (Divide & Conquer) T0 Time State FSM Most instructions follow same basic sequence Differ only in detailed execution sequence Time State FSM can be parameterized by opcode and AC states T1 Wait/ T2 Wait/ T3 Wait/ T4 Instruction State: stored in IR<15:14> BRN • AC  0/ T5 (LD + ST + ADD) • Wait/ T6 ³ BRN + (ST • Wait)/ Condition State: stored in AC<15> (LD + ADD) • Wait T7 CS 150 - Spring 2007 – Lec #18 – Mid #2 Review - 12

13. Jump Counters Pure Jump Counter NOTE: No inputs to jump state logic Logic blocks implemented via discrete logic, PLAs, ROMs CS 150 - Spring 2007 – Lec #18 – Mid #2 Review - 13

14. Jump Counters Hybrid Jump Counter Load inputs are function of state and FSM inputs CS 150 - Spring 2007 – Lec #18 – Mid #2 Review - 14

15. Jump Counters CLR, CNT, LD implemented via Mux Logic CLR = CLRm + Reset CLR = CLRm + Reset Active Lo outputs: hi input inverted at the output Note that CNT is active hi on counter so invert MUX inputs! CS 150 - Spring 2007 – Lec #18 – Mid #2 Review - 15

16. Branch Sequencers 4 Way Branch Sequencer 64 Word ROM I Mux N n C S Mux b a0 p o i a x11 Z a b a1 a b u n g a b x10 Y t a b a2 t n x01 X s Z Y a3 W X r a x00 W a4 o l a5 l s state Current State selects two inputs to form part of ROM address These select one of four possible next states (and output sets) Every state has exactly four possible next states CS 150 - Spring 2007 – Lec #18 – Mid #2 Review - 16

17. Branch Sequencers Alternative Horizontal Implementation Input MUX controlled by encoded signals, not state Much fewer inputs than unique states! In example FSM, input MUX can be 2:1! Adding length to ROM word saves on bits vs. doubling words Vertical format: (14 + 4) x 64 = 1152 ROM bits Horizontal format: (14 + 4 x 4 + 2) x 16 = 512 ROM bits CS 150 - Spring 2007 – Lec #18 – Mid #2 Review - 17

18. Vertical Microprogramming Branch Jump Compare indicated signal to 0 or 1 Register Transfer Source, Destination, Operation 10 ROM Bits CS 150 - Spring 2007 – Lec #18 – Mid #2 Review - 18

19. Vertical Programming Controller Block Diagram CS 150 - Spring 2007 – Lec #18 – Mid #2 Review - 19

20. Design/Reverse Engineering • Design Procedure: Specification --> Abstract Design --> Concrete Implementation • E.g., “What the state machine is supposed to do” to state diagram to jump counter implementation • Reverse Engineering: Concrete Implementation -->Abstract Design --> Specification • E.g., Jump counter implementation to state diagram to “what the state machine is supposed to do” CS 150 - Spring 2007 – Lec #18 – Mid #2 Review - 20