Foundation v1.5 Enhancements

1. Foundation v1.5Enhancements Version 2.0

2. New Features in Foundation F1.5 • Integration with Express and Implementation Tools via API mechanisms • Full Verilog Support • New Look and Feel for Project Manager • New Device Support • Virtex • XC9500XL • SpartanXL • Improved Synthesis Engine • Improved Implementation Engine

3. Express Integration • Emulation of Express look and feel in Files tab and Versions tab • Local menus • Files tab source status markers (check, ?, X) • Files tab entities display • Versions tab Functional/Optimized Structure and entities display • However, some changes consciously made to improve usability • Example: some changes in local menus • Example: dialog box option “assertion levels” (I.e. “Do not insert I/O pads” changed to “insert I/O pads”) • Full Constraint Manager and Timing Tracker implementation

4. Implementation Tools Integration • Most Design Manager functions are available from Project Manager • Version, Revision actions available via local menus, pull-down menus, and Flow Diagram automation • Ancillary Xilinx tools (e.g., Floorplanner, EPIC, etc.) are in Tools > Implementation pull-down menu • “Interactive” Flow Engine can be invoked on any Revision

5. Full Verilog Support • State Editor can now generate Verilog behavioral code • Full HDL Editor support • Color coding • Language Assistant • Syntax checking • Schematic Editor • Verilog modules (macros)

6. Project Manager • PCM is now truly “Mission Control” for Foundation • Express GUI and Design Manager no longer required in most cases (these are still provided in “Xilinx Foundation Series > Accessories” folder) • Menus re-organized for ease of use and support of integrated synthesis and implementation functionality

7. Files Tab (HDL Flow) • HDL files’ entities shown via Express API • Status of each HDL file’s Analysis shown • Local Menus provide Power User functions

8. Versions Tab (HDL Flow) • Displays both Express Elaborated/Optimized Structures and Xilinx Versions/Revisions • Symbology indicates elaboration/optimization results (i.e., x, exclamation point, checkmark) • Local menu pick for FE.LOG • Interactive Flow Engine can be invoked on any Revision at any time

9. More on HDL Flow’s Versions Tab • Top-level item in Tab corresponds to Express Elaboration and Xilinx “Version” • Multiple Versions can exist • A different package/speed within the same architecture can be selected without re-synthesizing (results in a new Revision) • Retargeting the design to a different architecture means you should re-synthesize (which means a new Version will be created) • “Revision” item corresponds exactly to Design Manager “Revision”

10. Versions Tab for Schematic Flow • Top-level object corresponds to “xproj” directory • Target family determined by File>Project Type dialog setting (as it was in F1.4) • Changing Project Type will attach new Unified Library to Project; subsequent Implementations will use the new Family

11. Versions Tab: Local Menus(HDL Flow) • Functional Structure Menu Provides Access to Express Constraint Manager • Optimized Structure Menu Includes Pick for Express Timing Tracker • Context-sensitive Local Menu Picks for Express Pre- and Post-Optimized Reports

12. Completely Revamped Flow Diagram • New “Phase Box” Design Step Grouping • Some Phases contain individual tool buttons • Flow Progress Indicators • Flow-sensitive Diagram Layout • Schematic Flow’s diagram does not have Synthesis Phase • New Flow Automation Single-action Phase button Multiple tool Phase button

13. “Pull” Model • Implemented for Synthesis, Functional Simulation, and Implementation Phase Boxes • Design will be “pulled through” the required processing steps to bring it to point that user selects

14. Synthesis/Implementation Dialog • This dialog is used for both Synthesis and Implementation Phase • Invoked from Files or Versions tab, from the Sythesis or Implementation pull-down menus, or as a result of selecting the Synthesis, Simulation, or Implementation Phase boxes • Depending on how it’s invoked, one section or the other may be grayed out

15. Messages/Reports • Express GUI tabs implemented in Console area • Xilinx Report Browser available via Reports Tab • “Implementation Log File” (FE.LOG) also shown

16. “Project” Pull-down Menu • Source files are automatically analyzed when added to Project • Single-point Version/Revision Management • “Clear Implementation Data” deletes all synthesis and implementation data and directories (but source files remain)

17. “Synthesis” and “Implementation” Pull-down Menus • Synthesis Menu Provides Design-Global Functions Plus a Few “Expected” Items • “local” functions are provided via local (right-mouse-button) menus • Shown in HDL Flow only • Implementation Menu Provides: • Duplicates Implementation Phase Button and “Implement” local menu pick • Invokes Xilinx Report Browser • Invokes Project Options dialog

18. “Tools” Pull-down Menu • Tools grouped into Phases • Implementation menu includes Pin Locking items (single command to lock pins) • Programming Tools are grayed out if not applicable to current architecture

19. What’s New in the Express Synthesis Engine • Integrated project management as discussed earlier • New architecture support • Virtex • Addition of some VHDL ‘93 constructs • end keyword - component keyword • is keyword - labels on assignments • T’image(X) - block in generate • alias keyword - array slices with others • Addition of other HDL constructs • rising_edge / falling_edge • ‘else • hex, octal and binary for std_logic_vectors

20. What’s New in the Express Synthesis Engine • New State Machine Synthesis Options • FSM Encoding Style • One Hot • Binary • FSM Extraction Method • Safest (all possible states) • Smallest (defined states only)

21. What’s New in the Implementation Engine • No License or Hardware Key Required • Express configurations require FlexLM • Software Run Time Enhancements • Significantly faster timing-driven place & route • Netlist translation and timing annotation steps 6 to 10 times faster than in v1.4 • New Timing Analysis Algorithms • designed to handle larger numbers of timing paths than in previous releases (critical for supporting the new, very large Virtex devices) • Design-aware Constraint Editor for schematic designs • New FPGA Floorplanner

22. More New Features • Integrated Installation Program • Installs Design Entry, Synthesis, and Implementation components (1 CD) • Each Part Family selection will install both the applicable schematic symbol library and the Implementation data files automatically • DynaText docs are on a separate CD • New Interactive (Macromedia) demo/introduction

23. Application Enhancements Version 2.0

24. Schematic Editor • Re-implemented Bus behavior • Complex buses • Bus editing now more similar to wire editing • Enhanced wire behavior • Selection, deletion • Autowiring • Rubberbanding • Local Menus (e.g., right-click > Hierarchy Push, copy/paste, Symbol Properties, etc.)

25. Schematic Editor (continued) • “SC Symbols” dialog box enhanced - Project components are listed separately from Unified Library comps • “Replace Symbol” option now has a drop-down selector from which to pick new symbol • Symbol attributes can now be moved directly (no need to bring up Properties dialog) • Multi-level undo (5 levels) • Copy/Paste enhancement: objects to be pasted are visible as copy buffer is moved around on the schematic • Enhanced Coregen 1.5 interface (i.e., symbol generation)

26. HDL Editor • New “Insert File” item in Edit menu • Provides easy method for insertion of LogiBLOX and CoreGen-created instantiation templates • Verilog syntax checking, color-coding, language templates, Schematic Flow macro synthesis • VHDL Language Assistant templates updated to be Express-compliant

27. Gate-Level Simulator • Virtex LUT support • New Simulation Script Wizard • invoked either at Script Editor start-up or from Script Editor’s Tools menu • Memory allocation tuning to support larger netlists • Signal Selection dialog “Search” feature enhanced • New “Enable Global Netlist Analysis” feature • can speed up simulation if disabled (not always needed) • Project-specific • See Whatsnew.HLP for more detail

28. Script Wizard • A new alternative to using the Simulation Macro Assistant

29. Script Wizard Resulting Script

30. Migration of F1.4 Designs Into F1.5 • No automatic conversion is done • F1.4, XACT 6 Projects are opened in their native Project Type • Automatic determination of proper Flow (Schematic or HDL) • Customers with existing designs that contain X-VHDL (Metamor) blocks may wish to keep Metamor installed for support of those designs • Metamor can be installed as a standalone component from F1.4 Design Entry Tools CD

31. $4995 Unequaled ValueFoundation Series Promotional Pricing $95 $495 $3995 X $7995 NOTE: Promotional Pricing Good Through 12/30/98

32. Foundation Series Product Roadmap Now Shipping! Nov 1998 Mid 1999 * * F1.5 F1.5i / F1.5J F2.1 • Foundation Ease-of-Use enhancements • Multi-media “Quick-Tour” demo • Embedded FPGA Express • Unified Project Mgmt. • Plug-and-Play HDL Simulation solutions • Advanced Performance Features • Timespec Constraint Editor • Floorplanner • Virtex (Beta), 9KXL, 4KXLA, SpartanXL device support • Foundation Ease-of-Use enhancements • Internet Access • New HDL templates • Advanced Performance Features • Express 2.1.3 synthesis • Production Virtex support • Latest device packages and Speed Grades • Japanese Localization • Next Generation Design Environment • HDL Centric Design Entry & Project Management • Improved Simulator Capacity / Performance • Foundation Ease-of-Use enhancements • Improved Push-Button Automation • Improved Error Navigation • Robust Version Control • CPLD Floorplanner * Regular scheduled Xilinx Software service packs are now distributed via the web.

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