EEL 3705 / 3705L Digital Logic Design

1. EEL 3705 / 3705LDigital Logic Design Fall 2006Instructor: Dr. Michael Frank Lecture Module #7: Lab #2 Prep & Karnaugh Maps M. Frank, EEL3705 Digital Logic, Spring 2007

2. Topics for Today (Wed. 1/24) • Administrivia: • Don’t forget, “Reading Assignment #1” is due Tuesday. • Turn in your lab report from lab #1 in this week’s labs. • Lab #2 pre-lab report is due in lab starting next Tuesday. • Use lab time this week to catch up & get an early start on lab #2. • YOU ARE REQUIRED TO ATTEND THIS WEEK’S LABS! • A HW#1 will hopefully be posted shortly! • Homeworks are generally due 1 week after they are assigned. • Today’s Lecture: • Lab #2 preparation • Combinational logic synthesis example • Schematic entry, more on simulation • Common subexpression elimination • Further logic optimization using Karnaugh maps • Postponed to Fri. or Mon.: • Radix (Base) Conversion Techniques M. Frank, EEL3705 Digital Logic, Spring 2007

3. Example Logic Synthesis Problem • Design an efficient logic circuit that will, for any input integer n in the range 2-15, output the largest integer k<n such that k divides n (with no remainder). • To solve such a problem, first, design and describe an explicit representation of the input-output relation as a Boolean function, • and then synthesize and optimize a combinational circuit to compute the desired function. • Typical steps in such a process: • Design input interface specifications • Design output interface specifications • Design functional specifications (truth table) • Synthesize the logic • Optimize the logic M. Frank, EEL3705 Digital Logic, Spring 2007

4. Design Functional Specifications • Start by tabulating the input-output relation: 3 1 5 1 2 1 1 6 3 1 1 7 4 5 M. Frank, EEL3705 Digital Logic, Spring 2007

5. Design Input Encoding • How many input bits are needed, if we wish to be able to uniquely encode any one of the allowed input values? • What names shall we give to the different input bits? • How will each of the individual input values be represented as a list of values of those bits? • Are there any possible lists of input bit-values that do not correspond to any of the legal input values? M. Frank, EEL3705 Digital Logic, Spring 2007

6. Design Output Encoding • How many different possible output values are there? • What is the minimum number of bits required to uniquely represent each possible output? • Name the output bits. • How will the particular outputs be encoded? There are seven of them: {1, 2, 3, 4, 5, 6, 7}. M. Frank, EEL3705 Digital Logic, Spring 2007

7. Next steps… • Write down the complete truth table… • Use “don’t care’s” as appropriate. • Commonly seen notations: “-”, “d”, or “x” • For each 1-bit Boolean function (output column), • synthesize a sum-of-minterms or product-of-maxterms expression for the function • Finally, simplify these expressions using any of several techniques… • Common subexpression elimination • Combining logically adjacent terms (K-maps help here) • many other manipulations are generally possible M. Frank, EEL3705 Digital Logic, Spring 2007

8. Today’s Lecture (Fri. 1/26) • New announcements: • If your TA gave you approval to submit late or revise your lab #1 report or pre-lab report, complete this by midnight Monday. • Turn in online through assignment link on Blackboard. • This is a final deadline, since I will be posting a Lab 1 report example early Tuesday. • So you can see it before turning in pre-lab 2. • Today’s Lecture: • Continue lab #2 preparation: • Review combinational logic synthesis example from last time • Schematic entry tips: Bussed wires, logic-gate megafunctions • Combining logically adjacent terms using Karnaugh maps • Postponed to Monday: • How to build a hierarchical design in Quartus • More K-map examples? • Radix (Base) Conversion Techniques M. Frank, EEL3705 Digital Logic, Spring 2007

9. Complete the Functional Specification • Write out the truth table… • Here, we’re using “d” to mean “don’t care” • I.e., any output value is acceptable M. Frank, EEL3705 Digital Logic, Spring 2007

10. Compose the SoP/PoS Formulas • Sum-of-products / product-of-sums • Generally speaking, • If there are few 1’s, then SoP will be simpler • If there are few 0’s, then PoS will be simpler • For this problem: • k2 – 5 ones, 9 zeros – Try SoP • k1 – 5 ones, 9 zeros – Try SoP • k0 – 11 ones, 3 zeros – Try PoS M. Frank, EEL3705 Digital Logic, Spring 2007

11. SoP/PoS Formulas • Here, each term is annotated above with its propositional meaning: n = 8 n = 10 n = 12 n = 14 n = 15 n = 4 n = 6 n = 9 n = 12 n = 14 n≠ 4 n≠ 8 n≠ 12 M. Frank, EEL3705 Digital Logic, Spring 2007

12. Circuit Corresponding to Equation for k0 • One problem with this approach: • Gates with large numbers of inputs tend to be large (costly) and slow! • Thus, this approach does not scale well to functions with very large numbers of variables and terms. M. Frank, EEL3705 Digital Logic, Spring 2007

13. Techniques for Combinational Logic Optimization M. Frank, EEL3705 Digital Logic, Spring 2007

14. Goals of Circuit Minimization • (1) Minimize the number of primitive Boolean logic gates needed to implement the circuit. • Ultimately, this also roughly minimizes the number of transistors, the chip area, and the cost. • Also roughly minimizes the energy expenditure • among traditional irreversible circuits. • This will be our focus. • (2) It is also often useful to minimize the number of combinational stages or logical depth of the circuit. • This roughly minimizes the delay or latency through the circuit, the time between input and output. • Note: Goals (1) and (2) are often conflicting! • In the real world, a designer may have to analyze and optimize some complex trade-off between logic complexity and latency. M. Frank, EEL3705 Digital Logic, Spring 2007

15. Minimizing Circuits Subtopics: • Combining logically adjacent terms using Karnaugh Maps (CIO #5) • Focus of this lecture • Don’t care conditions • Common subexpression elimination • The Quine-McCluskey Method • Optional; not covering this semester • Simplification using arbitrary Boolean identities • Not covering in depth this semester in lecture M. Frank, EEL3705 Digital Logic, Spring 2007

16. Minimizing DNF Expressions • Using DNF (or CNF) expressions guarantees that you can always find some circuit that implements any desired Boolean function. • However, the resulting circuit may be larger than is really required! • We would generally like to find the smallest sum-of-products expression that is equivalent to a given function. • This will yield a fairly small circuit. • However, circuits of other forms (not either CNF or DNF) might be even smaller for complex functions. • In general, finding the absolute smallest circuit is an NP-hard problem – not tractable for very complex functions M. Frank, EEL3705 Digital Logic, Spring 2007

17. Logic Simplification Technique #1:Common Subexpression Elimination • One general way to simplify any kind of algebraic expression is by combining repeated subexpressions • So they will only be computed once • Example: Consider the expression for k2 • Some repeated subexpressions are indentified below • We can then create these “temporary variables:” • And then substitute them into the k2 expression: M. Frank, EEL3705 Digital Logic, Spring 2007

18. Equation with Common Subexpressions Combined, Rendered as a Circuit Reduced width of AND gates,but now we need two levels of them… M. Frank, EEL3705 Digital Logic, Spring 2007

19. Logic Simplification Technique #2:Combining Logically Adjacent Terms • We can eliminate terms from SoP formulas using the Boolean identity: • So, any two product terms that differ only in the form (complemented or uncomplemented) of a single literal can be combined together, • while eliminating that literal from them! • This reduces both the number of terms, and the size of each term! • It is a big win. M. Frank, EEL3705 Digital Logic, Spring 2007

20. Lecture of Mon., 1/29/07 • Announcements: • Any late or revised lab #1 reports must be submitted online tonight, no exceptions! • An example “perfect” report will be posted tomorrow at 6 AM. • Pre-lab reports for lab 2 are due at the start of your lab section this coming week (Tue.-next Mon.) • Today’s Lecture: • Continue lab #2 preparation: • Continue with Karnaugh map examples • How to build a hierarchical design in Quartus • Grouping signals for simulation • Postponed to Wed.: • Radix (Base) Conversion Techniques M. Frank, EEL3705 Digital Logic, Spring 2007

21. Example of Combining LogicallyAdjacent Terms in Formula for k2 n = 10 n = 8 n = 12 n = 15 n = 14 (Play the slideto see the orderof steps.) n {8, 10, 12, 14} n {14, 15} case n=14 is covered twice,but this does not matter! M. Frank, EEL3705 Digital Logic, Spring 2007

22. Let’s now see how to speed up the simplification process using K-maps • To the right is the truth table again for just the one output bit k2 • We’ll now see how to use it to quickly combine logically adjacent terms using a Karnaugh map • This is one of the officialcourse objectives! It will be tested on exams! M. Frank, EEL3705 Digital Logic, Spring 2007

23. K-map for k2 example n1=0 n1=1 • Prime implicants (PIs, circled) are maximal-sized groupings of 1’s • Can’t be further doubled w/o including zeros • PIs correspond to the simplest product terms • w the most variables eliminated • Essential prime implicants (EPIs, red) are PIs that cover 1s that no other PIs cover • These PIs must be included in your cover. 0 d d 0 n3=0 0 0 0 0 n2=1 1 1 1 0 n3=1 1 1 0 0 n0=1 M. Frank, EEL3705 Digital Logic, Spring 2007

24. Circuit for Simplified k2 Equation • Structure corresponds directly to simplified formula… • Uses just one 2-input AND, one 3-input AND (inputs drawn as a bus),and one 2-input OR. M. Frank, EEL3705 Digital Logic, Spring 2007

25. Top-Level Block Diagram for Divisor-Finding Circuit, So Far Symbols for subcircuitswe already created Should pass Analysis but not Synthesis (since divisor1 block has not been functionally defined, to Quartus, it cannot be synthesized) bus line signalconduit Block – placeholderin schematic forsubcircuit not yetdesigned node line M. Frank, EEL3705 Digital Logic, Spring 2007

26. Truth Table and K-map for k1 n1=0 n1=1 0 d d 0 n3=0 1 0 1 0 n2=1 1 0 1 0 n3=1 0 0 1 0 n0=1 M. Frank, EEL3705 Digital Logic, Spring 2007

27. Optimized SoP circuit for k1 M. Frank, EEL3705 Digital Logic, Spring 2007

28. Truth Table and PoS K-map for k0 n1=0 n1=1 1 d d 1 n3=0 0 1 1 1 n2=1 0 1 1 1 n3=1 0 1 1 1 n0=1 M. Frank, EEL3705 Digital Logic, Spring 2007

29. Optimized PoS circuit for k0 • The big circuit on slide 12 has been simplified to a single OR gate! M. Frank, EEL3705 Digital Logic, Spring 2007

30. Completed Top-Level Schematic M. Frank, EEL3705 Digital Logic, Spring 2007

31. Another Possible Top-Level Design • Instead of dividing up the design by output bits, • we could have divided it up into the first and second levels of gates… AND gates for k2 mintermsand k1 mintermsgo in here OR gates for combining minterms 4 div2 4 Mintermgenerator Mintermcombiner num3..0 div1 div3..0 div0 Maxtermgenerator Maxtermcombiner Not needed inour example – nonegated literalsin maxterms The single OR gatefor k0 goes in here AND gates for combiningmaxterms (none in this case) M. Frank, EEL3705 Digital Logic, Spring 2007

32. Most Frequent Mistakes in Doing K-maps • Labeling rows/columns in wrong order • Don’t use the normal binary order 00,01,10,11 (wrong); use 00,01,11,10 (right) • Copying truth table column into the K-map rows & columns in the wrong order • It may help to first sequentially number all of the cells. • Drawing groupings of shapes other than rectangles, or that don’t contain a power of 2 cells (2,4,8,etc.), or that contain some 0s. • If group is not rectangular, 0’s are contained in it, or the number of cells is not equal a power of 2, then it does not correspond to any valid product term! • Drawing groupings that are not the largest possible! • If a group can be combined with a neighboring group, then it must be combined, in order to produce an equation with fewer (and smaller) product terms • Failing to consider groupings that go off the edges of the board • left-right and/or top/bottom edges • Failing to take full advantage of don’t-cares in one’s map • They are wildcards; use some as 1s if this helps increase the size of existing groupings • Failing to select an optimal cover • Often the EPIs will not cover all the 1s, and you may also have to select from among various different possible sets of the non-essential PIs. Some sets may be smaller than others! Choose the one with the fewest PIs (fewest product terms) in it. M. Frank, EEL3705 Digital Logic, Spring 2007

33. Tips on Schematic Entry with Subcircuits • Create each important subcircuit in its own individual .bdf file (block diagram file). • Make sure you include all of its I/O ports. • Select menu item “File -> Create/Update -> Create Symbol Files for Current File.” • This creates the .bsf file (block symbol file) • This contains a drawing of a “block” icon for your circuit, with input/output ports. • Make sure the file is added to your project, and then in the top-level file for your project, M. Frank, EEL3705 Digital Logic, Spring 2007

34. Screenshot showing how we select the icon for our own custom logic block to insert M. Frank, EEL3705 Digital Logic, Spring 2007

35. Karnaugh Maps (K-Map) A K-Map is a graphical representation of a logic function’s truth table from which one can quickly calculate the simplest sum-of-products (or product-of-sums) representation of the function M. Frank, EEL3705 Digital Logic, Spring 2007

36. Relationship to Venn Diagrams M. Frank, EEL3705 Digital Logic, Spring 2007

37. Relationship to Venn Diagrams M. Frank, EEL3705 Digital Logic, Spring 2007

38. Relationship to Venn Diagrams a b M. Frank, EEL3705 Digital Logic, Spring 2007

39. Relationship to Venn Diagrams a b M. Frank, EEL3705 Digital Logic, Spring 2007

40. Relationship to Venn Diagrams M. Frank, EEL3705 Digital Logic, Spring 2007

41. Two-Variable K-Map M. Frank, EEL3705 Digital Logic, Spring 2007

42. Three-Variable K-Map Note: The bit sequences must alwaysbe ordered using a Gray code! M. Frank, EEL3705 Digital Logic, Spring 2007

43. Three-Variable K-Map Note: The bit sequences must always be ordered using a Gray code! M. Frank, EEL3705 Digital Logic, Spring 2007

44. Three-Variable K-Map Note: The bit sequences must always be ordered using a Gray code! Edges are adjacent M. Frank, EEL3705 Digital Logic, Spring 2007

45. Four-variable K-Map Note: The bit sequences must be ordered using a Gray code! Note: The bit sequences must be ordered using a Gray code! M. Frank, EEL3705 Digital Logic, Spring 2007

46. Four-variable K-Map M. Frank, EEL3705 Digital Logic, Spring 2007

47. Four-variable K-Map Edges are adjacent Edges are adjacent M. Frank, EEL3705 Digital Logic, Spring 2007

48. Plotting Functions on the K-map SOP Form M. Frank, EEL3705 Digital Logic, Spring 2007

49. Canonical SOP Form Three Variable Example using shorthand notation M. Frank, EEL3705 Digital Logic, Spring 2007

50. Three-Variable K-Map Example Plot 1’s (minterms) of switching function 1 1 1 1 M. Frank, EEL3705 Digital Logic, Spring 2007