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[M2] Traffic Control

[M2] Traffic Control. Group 2 Chun Han Chen Timothy Kwan Tom Bolds Shang Yi Lin Manager Randal Hong. Overall Project Objective : Dynamic Control The Traffic Lights. Wed. Sep 29. Status. Design Proposal Chip Architecture Behavioral Verilog Implementation

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[M2] Traffic Control

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  1. [M2] Traffic Control Group 2 Chun Han Chen Timothy Kwan Tom Bolds Shang Yi Lin Manager Randal Hong Overall Project Objective : Dynamic Control The Traffic Lights Wed. Sep 29

  2. Status • Design Proposal • Chip Architecture • Behavioral Verilog Implementation • Size estimates (Refined) • Floorplanning (Refined) • Behavioral Verilog simulated • Gate Level Design • Component Layout/Simulation • Chip Layout • Complete Simulation

  3. Traffic Flows ARM 1 Sensors (Blue) To detect the car entered ARM 2 Sensors (Red) To detect the car leaved

  4. Traffic Light Flow Phase C PED ARM 1 Red Green (Straight + Right) Y Red+Green(Left) Y Red Green Y Red Green (Straight + Right) Y Red+Green(Left) Y ARM 2 Phase A Phase B Phase A Phase B ARM1 ARM1 ARM2 ARM2 We define three phases (A,B,C) for different operations. Whenever pedestrian push the button, then this light will insert in the end of this cycle.

  5. FSM For Lights Initial SW = 0 SW =0 ARM = 0 ARM = 1 G.R R.G T=15 SW – Switch light G – Green R – Red Y – Yellow T – Time for Yellow PED – Pedestrian SW = 1 SW = 1 T = 2 PED = 0 T = 2 PED = 0 T < 2 Y.R R.Y T < 2 T = 2 T = 2 SW = 0 R+Left.R R.R+Left SW =0 Blink SW = 1 SW = 1 T < 5 T<= 2 Y.R T=10 R.Y T<= 2 Clear (1bit) SW (1bit) ARM1 [1:0] PED = 1 T = 2 PED = 1 T = 2 ARM (1bit) FSM PED ARM2 [1:0] PED(1bit) PED(1bits) CLK Complete(1bits) T<10

  6. reset Pedestrian For Green light Control Hold until n1 or n2 changes For Pedestrian For Red + Left Light favors n1 or n2 ? Yes Yes No Light favors arm1 or arm2 ? n1 n2 T>= Rp ? Yes Yes T<r1? T<r2? n1 n2 Reset T = 0 No No T<rleft? Yes T<rleft? Yes T>= R1? T>= R2? No No Yes Yes No No n1 not change in T = 5? Yes n2 not change in T = 5? Yes Yes n2=0? n1=0? No No No No No Yes Yes T>= Rleft? T>= Rleft? Yes Yes No f2<=0? f1<=0? No No Switch Light n1, n2 :# of cars T :Time spent in this phase Ri , ri : Max. and Min. time for each phase fi : the control function f1 = α1*n1+ β1 – n2 f2 = α2*n2+ β2 – n1

  7. FPU Multiplier

  8. FPU Mult • Adder • Add exps • Mult • Multiply significants • Mtmp + Leadshift • Determine possible ovf and normalize • SigshiftY, SigY, SignY • Rounding more or less • Determines sign • Special Cases – NaN/inf

  9. FPU Multiplier Hardware • 4-bit adder(RCA) – 112 • Sequential Multiplier(8-bit) • 8-bit RCA – 224 • 8 2-input AND gates – 48 • 3x8bit Registers – 336 • 4-bit decrementer – 142 • 17 Bit Barrel Shifter -5780!!!(Programmable) • 12 bit comparator – 408 • Other Logic gates – 14

  10. FPU Mult. Hardware cont. • Special Case Logic(NaN/Inf) • 3x4-bit comparators – 0* (use prev 12 bit comp) • 2x7-bit comparator – 0* • 12-bit comparator – 0* • 2x12-bit MUX – 96 • Other logic gates – 56 • Overflow Mult Logic • 3x4 bit comparator – 0* • 12 bit comparator – 0* • 2x 2-bit MUX – 16 • Other Logic – 60 • 1x 8-bit MUX – 32 • 1x12-bit MUX – 48

  11. FPU Mult Hardware cont. • sigY • 8-bit incrementer – 112 • 4-bit incrementer - 56 • 2x12-bit MUX – 96 • 8-bit comparator - 0* • 12-bit Shifter – 0* • 1-bit MUX – 4 • 4-bit mux - 16 • Other Logic – 12 • SignY • 12-bit comparator – 0* • 4-bit comparator – 0* • Leading Zeroes 12-bit – 340

  12. FPU Mult. Hardware cont. • Mtmp • 16-bit MUX – 64 • 4-bit MUX – 16 • 1-bit MUX - 4 • 4 bit adder(RCA) – 112 • 16 Bit shifter – 0* • Other logic -86 • Leadshift • 2x4-bit Comparator – 0* • 2x16-bit shifter – 0* • 2x16-bit MUX – 128 • 2x4-bit MUX – 32 • Other logic -34 • Total • 8484(2704 excluding barrel shifter) Transistors with some reuse(Reg/Mux not added for reuse operations)

  13. Addition/Subtraction • Shifting • Shift significants and alter exp • Inv Signal if necessary(Add/Sub) • Does Add/Sub in Add/Sub • Does sign Recognition • Make_pos • Possibly a negative significant, thus make it a positive significant if necessary otherwise filter threw • Overflow • Rounding • Special Cases

  14. FPU Add/Sub hardware • Special Cases-0* • Other Logic – 40 • Shifting • 17-bit barrel shifter – 0* • 5x 5-bit comparators – 0* • Other logic – 600 (lot of gate logic to choose shifting and get diff of exp(with adders)) • LeadingZeros12 – 0* • 3x8-bit adder

  15. FPU Add/Sub hardware • Add/Sub • 12-bit RCA –336 • Logic Gates/Arrays – 300 • 2:1 12-bit MUX – 48 • MakePos • 12-bit RCA – 336 • Logic Gates – 426 • Zero Res • 12-bit comparator – 0* • Logic Gates – 208

  16. FPU Add/Sub Hardware • Overflow Manipulation • 2x17 bit barrel-shifter – 0* • 4-bit RCA Adder -112 • 4-bit Comparator – 0* • 2:1 12 bit MUX – 48 • Other logic to determine ovf – 300 • Rounding • 2x17 bit barrel-shifter -0* • Other logic - 576 • 2x12-bit adder – 672 • 4-bit adder -112 • 4-bit comparator – 0*s • Total -3474

  17. FPU Total Transistor Count • Addition/Sub – 3474 • Multiplier – 8484 • Extra Muxing + Registers for Reuse – 1000? • Total- 12958 • Save more adders?

  18. Block Diagram 2:1 MUX 120 Reg X 10 β 120 12 Reg X 10 12 2:1 MUX 12 12 12 12 12 16:1 MUX 12 12 X 10 1:16 De-MUX ROM q0,q1: X2 n0 n1 8 ENTER 12 X 9 β n0 12 12 n1 β 12 q0 12 12 q1 F to comparator Accum 8 Reg 8 Conv.F 12 Q_len 12 12 ½ 12bit 4 s0,s1: X2 Sel FPU Reg. n_avg 12 temp 12 192 8 OUT or LEFT 12 X 1 12 12 s0 αn0-n1 12 12 s1 αn0 Accum 8 Reg 8 Conv.F 12 α0 q0-s0 12 α1 12 q1-s1 N_avg Q(αn0-n1) αn0-n1 αn0 12 2:1 MUX α0,α1:X2 q0-s0 4 User Input 12 q1-s1 12 Reg Q(αn0-n1) Sel ROM 2 4 Sel_FPU Sel 2:1 MUX 8 X 8 : to comparator R,r, RL,rl for arm1&2 64 64 User Input R,r Reg 12 64 12 ½ 12 ROM 12 12 12 12 User Input 1/Q 12 12 Reg 12 2:1 MUX 8:1 MUX 2 ARM 1 1 1 PED 8 X 2 8 8 X 8 8 PED Input Reg SW 1 2 ARM 2 FP. Compar INT. Compar 1 ARM 1 FSM FSM 1 PED. CLK 1 1 PED 8 X 2 8 X 8 Reg PED 1 8 8 CLK 1 Complete 1 1 Clear 1

  19. T : 96 2:1 MUX T : 1680 X 2 120 Reg X 10 β 120 12 Reg X 10 12 2:1 MUX 12 T : 1440X2 12 12 T : 166 12 12 16:1 MUX 12 12 X 10 T : 1440 T : 12k T : 1680 1:16 De-MUX ROM T : 3336 X 2 q0,q1: X2 n0 n1 8 ENTER 12 X 9 β n0 12 12 n1 β 12 q0 12 12 q1 F to comparator Accum 8 Reg 8 Conv.F 12 Q_len 12 12 ½ 12bit 4 s0,s1: X2 Sel FPU Reg. n_avg 12 temp T : 3336 X 2 12 192 8 OUT or LEFT 12 X 1 12 12 s0 αn0-n1 12 12 s1 αn0 Accum 8 Reg 8 Conv.F 12 α0 q0-s0 12 α1 12 q1-s1 N_avg Q(αn0-n1) αn0-n1 αn0 12 2:1 MUX α0,α1:X2 q0-s0 4 User Input 12 q1-s1 12 Reg Q(αn0-n1) Sel ROM 2 4 Sel_FPU Sel T : 334 2:1 MUX 8 X 8 : to comparator R,r, RL,rl for arm1&2 64 64 User Input R,r Reg 12 64 12 ½ 12 ROM 12 12 12 12 User Input 1/Q 12 12 Reg 12 2:1 MUX 8:1 MUX T : 2072 2 ARM 1 1 1 PED 8 X 2 8 8 X 8 8 PED Input Reg SW 1 2 ARM 2 FP. Compar INT. Compar 1 ARM 1 T : 14 FSM FSM 1 PED. CLK 1 1 PED 8 X 2 8 X 8 Reg PED 1 8 8 CLK 1 Complete T : 14 T : 344 T : 344 1 T : 448 X 2 T : 64 X 2 T : 5000 1 Clear 1 T : 460

  20. Transistor Count Estimates

  21. Input Get q0 q1 s0 s1 Input PED, CLK Give R,r Avg. q Reuse Control Light Compare T ½ , Q_L F , Ni FPU Output

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