# Learning to Design Counters - PowerPoint PPT Presentation

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Learning to Design Counters. Today: First Hour : Designing a Counter Section 7.2 of Katz’s Textbook In-class Activity #1 Second Hour : More on Counters Section 7.3 of Katz’s Textbook In-class Activity #2. Given the current state, and its inputs. What is its next state?.

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Learning to Design Counters

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## Learning to DesignCounters

• Today:

• First Hour: Designing a Counter

• Section 7.2 of Katz’s Textbook

• In-class Activity #1

• Second Hour: More on Counters

• Section 7.3 of Katz’s Textbook

• In-class Activity #2

Given the current state, and its inputs. What is its next state?

SRQQ+JKQQ+DQQ+TQQ+

0000000000

0010010101

0100101010

0110111111

100100

101101

110110

111111

### Recap: Flip Flops

0

1

1

0

0

1

0

0

1

1

X

X

0

1

0

0

1

1

1

0

0

0

1

1

X = that input is illegal

QQ+RSJKTD

00

01

10

11

RESET

TOGGLE

### Excitation Tables

Suppose we want to change from state Q = 1 to state Q+ = 0

X1

10

RESET or TOGGLE

What should be the input (excitation) for a

T flip-flop or a D flip-flop

to make this change?

J-K flip-flop

Why is JK = X1? Because either JK = 01 or JK = 11 will change state 1 to state 0. Similar reasoning yields the other entries.

Described by State Diagrams, much the same way that combinational logic circuits are described by Boolean Algebra.

### Synchronous Finite-State Machines

Current

State

New

State

Current Input(s)

Change of state happens only on the clocking event

### Example:3-bit Binary Up-Counter

001

001

010

010

000

000

Each circle corresponds to a state

The label inside each circle describes the state

011

011

111

111

Arrows represent state transitions

101

101

100

100

110

110

No labels on arrows, since the counter has no inputs

CurrentNext

StateState

C B A C+ B+ A+

0 0 0

0 0 1

0 1 0

0 1 1

1 0 0

1 0 1

1 1 0

1 1 1

000

100

011

101

110

001

010

111

### State Transition Table

The Table is equivalent to the Diagram

The “+” superscripts indicate new values.

0 0 1

0 1 0

0 1 1

1 0 0

1 0 1

1 1 0

1 1 1

0 0 0

State Transition Table

State Diagram

CurrentNext

StateState

C B A C+ B+ A+

0 0 0 0 0 1

0 0 1 0 1 0

0 1 0 0 1 1

0 1 1 1 0 0

1 0 0 1 0 1

1 0 1 1 1 0

1 1 0 1 1 1

1 1 1 0 0 0

### Picking a Flip-Flop

Let's use T F/Fs

How many do we need?

3

State Transition Table

Neat Fact: we could have picked any other type or more than one type

Excitation Table

QQ+T

000

011

101

110

### Flip-Flop Input Table

What T F/F inputs are needed to make them change to the next state?

CurrentNextFlip-Flop

StateStateInputs

C B A C+ B+ A+ TC TB TA

0 0 0 0 0 1

0 0 1 0 1 0

0 1 0 0 1 1

0 1 1 1 0 0

1 0 0 1 0 1

1 0 1 1 1 0

1 1 0 1 1 1

1 1 1 0 0 0

0 0 1

0 1 1

0 0 1

1 1 1

0 0 1

0 1 1

0 0 1

1 1 1

F/F Input Table

State Transition Table

C

B

CurrentFlip-Flop

StateInputs

C B A TC TB TA

0 0 0 0 0 1

0 0 1 0 1 1

0 1 0 0 0 1

0 1 1 1 1 1

1 0 0 0 0 1

1 0 1 0 1 1

1 1 0 0 0 1

1 1 1 1 1 1

A

0

0

0

1

1

1

1

0

0

1

1

1

1

1

1

1

1

1

TA

C

B

0

0

0

1

1

1

1

0

A

0

0

0

0

0

TB

1

1

1

1

1

C

B

0

0

0

1

1

1

1

0

A

0

0

0

0

0

TC

1

0

1

1

0

TA = 1

TB = A

TC = A•B

Re-drawn Table

+5V

QA

QB

QC

S

S

S

Q

Q

Q

T

T

T

CLK

CLK

Q

CLK

Q

Q

R

R

R

\Reset

Count

100

\Reset

Q

C

Q

B

Q

A

Count

TB = A

TA = 1

TC = AB

Timing Diagram

### Complex Counters

The generalized design process has four steps

1. Draw a State Transition Diagram

2. Derive the State Transition Table

3. Choose a Flip-Flop to Implement the Design

4. Derive the Flip-Flop Input Functions

Note: this list skips step 3 on page 341 of the Katz.

000

011

101

010

110

### Complex Counters

Design a counter with the sequence 000, 010, 011, 101, 110, and wrap

1. Derive the State Transition Diagram

State Diagram

CurrentNext

StateState

C B A C+ B+ A+

0 0 0

0 0 1

0 1 0

0 1 1

1 0 0

1 0 1

1 1 0

1 1 1

000

011

101

010

110

Note the use of Don't Care conditions

### 2. State Transition Table

Tabulate the Next State for each State in the Diagram

0 1 0

X X X

0 1 1

1 0 1

X X X

1 1 0

0 0 0

X X X

State Transition Table

State Diagram

QQ+T

000

011

101

110

### 3. Choose F/Fs

Suppose we choose T Flip-Flops to implement the design

Excitation Table

CurrentNextFlip-Flop

StateStateInputs

C B A C+ B+ A+ TC TB TA

0 0 0 0 1 0

0 0 1 X X X

0 1 0 0 1 1

0 1 1 1 0 1

1 0 0 X X X

1 0 1 1 1 0

1 1 0 0 0 0

1 1 1 X X X

Excitation Table

QQ+T

000

011

101

110

F/F Input Table

State Transition Table

0 1 0

X X X

0 0 1

1 1 0

X X X

0 1 1

1 1 0

X X X

C

B

CurrentFlip-Flop

StateInputs

C B A TC TB TA

0 0 0 0 1 0

0 0 1 X X X

0 1 0 0 0 1

0 1 1 1 1 0

1 0 0 X X X

1 0 1 0 1 1

1 1 0 1 1 0

1 1 1 X X X

A

0

0

0

1

1

1

1

0

0

0 1 0 X

X 0 X 1

TA = A·B·C + B·C

1

TA

C

B

1 0 1 X

X 1 X 1

0

0

0

1

1

1

1

0

A

TB = A + B + C

0

TB

1

0 0 1 X

X 1 X 0

TC = A·C + A·C

= A  C

C

B

Re-drawn Table

0

0

0

1

1

1

1

0

A

0

TC

1

TC = A  C

TA = A·B·C + B·C

TB = A + B + C

TB

B

TA

A

TC

C

S

S

S

Q

Q

T

Q

T

T

Q

Q

Q

CLK

CLK

CLK

\C

\B

\A

R

R

R

Count

\Reset

Excitation Table

For T F/F

TB

B

TA

A

TC

C

S

S

S

Q

QQ+T

000

011

101

110

Q

T

Q

T

T

Q

Q

Q

CLK

CLK

CLK

\C

\B

\A

R

R

R

Count

\Reset

### Do Activity #1 Now

Note: This is a just a cleaner way to sketch the circuit

Works properly in LogicWorks

When we work with hardware,

we have to explicitly wire these connections

111

000

110

001

010

101

100

011

State Diagram

### When a counter “wakes up”…

Random power-up states

• The counter may be in any possible state

• This may include skipped states

In the counter example from the previous lecture, states 001, 100, & 111 were skipped

It is possible that the random power-up state may be one of these

Can we be sure the counter will sequence properly?

Present

State

Toggle

Inputs

CBATCTBTA

000010

001101

010001

011110

100011

101011

110110

111110

Flip-Flop Input Functions

### Don't-Care Assignments

K-map minimization

The Xs for the Toggle Inputs were set by the K-maps to minimize the T Flip-Flop Input Functions

111

000

110

001

010

101

100

011

State Diagram

### Skipped State Behavior

Sequences from K-map minimization

When these K-map assignments are made for the Xs, it results in

001  100, 100  111, and 111  001

Therefore, the counter might not sequence properly

000

110

010

101

011

### Self-Starting Counter

111

001

100

A self-starting counter is one that transitions to a valid state even if it started off in any other state.

-t/RC

5e

+5

High threshold

t

Reset

Time

### Counter Reset Solution

Use a separate Reset switch

Power-ON Reset Circuit: Reset signal is 1 briefly while circuit is powered up. This signal is used to reset all flip-flops.

+5V

P

W

R

C

To FF

Resets

R

### Using other Flip-Flops

Just use the correct Excitation Table in setting up the flip-flop input function table.

The input functions must be appropriate for the flip-flop type (no bad input patterns).

QQ+JK

000X

011X

10X1

11X0

Q+ = J Q' + K' Q

J-K Excitation Table

### Example #1:J-K F/F

3-bit Counter: 0  2  3  5  6  0 …

Present

State

Next

State

Flip-Flop

Inputs

CBAC+B+A+JCKCJBKBJAKA

0X1X0X

XXXXXX

0XX01X

1XX1X0

XXXXXX

X01XX1

X1X10X

XXXXXX

000010

001XXX

010011

011101

100XXX

101110

110000

111XXX

Flip-Flop Input Functions

Fill in flip-flop input functions based on J-K excitation table

CB

CB

11

11

00

01

10

00

01

10

A

A

0 0 X X

X 1 X X

X X 1 X

X X X 0

0

0

Present

State

Next

State

Flip-Flop Input

Inputs

1

1

CBAC+B+A+JCKC JB KB JA KA

000010 0 X1X0X

001XXX X XXXXX

010011 0 XX01X

011101 1 XX1X0

100XXX X XXXXX

101110 X 01XX1

110000 X 1X10X

111XXX X XXXXX

JC

KC

CB

CB

11

11

00

01

10

00

01

10

A

A

X 0 1 X

X 1 X X

1 X X X

X X X 1

0

0

1

1

JB

KB

Flip-Flop Input Functions

CB

CB

11

11

00

01

10

00

01

10

A

A

0 1 0 X

X X X X

X X X X

X 0 X 1

0

0

1

1

JA

KA

= A

= A’

= A + C

= 1

= B C'

= C

+5V

C

B

A

A

J

Q

J

Q

JA

J

Q

CLK

CLK

CLK

\

A

C

K

Q

KB

K

Q

K

Q

\

C

\

B

\

A

Count

A

B

JA

KB

C

\

C

### J-K Flip-Flop Counter

Resulting Logic Level Implementation:

2 Gates, 10 Input Literals + Flip-Flop Connections

CBAC+B+A+DC DB DA

000010 0 10

001XXX X XX

010011 0 11

011101 1 01

100XXX X XX

101110 1 10

110000 0 00

111XXX X XX

### Example #2: D F/F

Simplest Design Procedure

D F/F inputs are identical to the next

state outputs in the state transition table

C+ B+ A+ columns are identical to DC DB DA columns

C

B

A

A

DA

D

Q

D

Q

DB

D

Q

CLK

Q

CLK

Q

CLK

Q

\

C

\

B

\

A

Count

\

C

B

DB

\

A

DA

\

C

\

B

### D Flip-Flop Counter

Resulting Logic Level Implementation:

3 Gates, 8 Input Literals + Flip-Flop connections

T F/Fs well suited for straightforward binary counters

But yielded worst gate and literal count for this example!

J-K F/Fs yielded lowest gate count

Tend to yield best choice for packaged logic where gate count is key

D F/Fs yield simplest design procedure

Best literal count

D storage devices very transistor efficient in VLSI

Best choice where area/literal count is the key

### Do Activity #2 Now

• Due: End of Class Today.NO EXTENSION TODAY

• RETAIN THE LAST PAGE(S) (#3 onwards)!!

• For Next Class:

• Bring Randy Katz Textbook, & TTL Data Book