Lecture 10
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Lecture 10. PLDs ROMs Multilevel logic. Read-only memories (ROMs). Two dimensional array of stored 1s and 0s Input is an address  ROM decodes all possible input addresses Stored row entry is called a "word" ROM output is the decoded word. n address lines. • • •. inputs.

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Lecture 10

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Lecture 10

Lecture 10

  • PLDs

    • ROMs

  • Multilevel logic


Read only memories roms

Read-only memories (ROMs)

  • Two dimensional array of stored 1s and 0s

    • Input is an address  ROM decodes all possible input addresses

    • Stored row entry is called a "word"

    • ROM output is the decoded word


Lecture 10

n address lines

• • •

inputs

memoryarray(2n wordsby m bits)

2n wordlines

decoder

outputs

• • •

ROMs


Like this pla example

A

B

C

A'B'C'

A'B'C

A'BC'

A'BC

AB'C'

AB'C

ABC'

ABC

ABCF1F2F3F4F5

000 0 0 1 1 0

001 0 1 0 1 1

010 0 1 0 1 1

011 0 1 0 1 0

100 0 1 0 1 1

101 0 1 0 1 0

110 0 1 0 1 0

111 1 1 0 0 1

F1

F2

F3

F4

F5

Like this PLA example

Think of as a memory-address decoder

F1 = ABC

F2 = A + B + C

F3 = A' B' C'

F4 = A' + B' + C'

F5 = A xor B xor C

0 1 0

Memory bits

0 1 0 1 1


Rom details

ROM details

  • Similar to a PLA but with a fully decoded and fixed AND array

  • Completely flexible OR array (unlike a PAL)


Rom details1

ROM details

+5V

Only one word line

is active at any time

n-1

2

2

decoder

1

0

n-1 0

Address

m-1 0

Outputs

Bit lines: Normally pulled high through resistor. If bit stores a zero, then

transistor pulls low when row is selected.


Two level logic using a rom

Two-level logic using a ROM

  • Use a ROM to directly store a truth table

    • No need to minimize logic

ABCF0F1F2F3

000 0 0 1 0001 1 1 1 0010 0 1 0 0011 0 0 0 1

100 1 0 1 1

101 1 0 0 0

110 0 0 0 1

111 0 1 0 0

You specify whether to store 1 or 0 in each location in the ROM

ROM8 words x 4 bits/word

ABCF0 F1 F2 F3

address

outputs


Roms versus plas pals

ROMs:

Benefits

Quick to design, simple

Limitations

Size doubles for each additional input

Can't exploit don't cares

PLAs/PALs:

Benefits

Logic minimization reduces size

Limitations

PAL OR-plane has hard-wired fan-in

ROMs versus PLAs/PALs


Example bcd to 7 segments

The problem

Input is a 4-bit BCD digit (A, B, C, D)

Need signals to drive a display (7 outputs C0 – C6)

c0

c1

c5

c6

c4

c2

c0 c1 c2 c3 c4 c5 c6

c3

BCD to 7–segmentcontrol-signaldecoder

A B C D

Example: BCD to 7-segments


Formalize the problem

Truth table

Many don’t cares

Choose implementation target

If ROM, we are done

Don't cares imply PAL/PLA may be good choice

Implement design

Minimize the logic

Map into PAL/PLA

Formalize the problem

ABCDC0C1C2C3C4C5C6

00001111110

00010110000

00101101101

00111111001

01000110011

01011011011

01101011111

01111110000

10001111111

10011110011

101XXXXXXXX

11XXXXXXXXX

Not all rows of the truth table are listed separately


Sop implementation

A

A

A

A

A

A

A

1 0 X 1

0 1 X 1 1 1 X X

1 1 X X

1 0 X 1

0 0 X 0 0 0 X X

1 1 X X

1 1 X 1

0 1 X 1 0 0 X X

0 1 X X

1 1 X 1

1 1 X 1 1 1 X X

0 1 X X

0 1 X 1

0 1 X 1 1 0 X X

1 1 X X

1 1 X 1

1 0 X 1 1 1 X X

1 0 X X

1 0 X 1

0 1 X 0 1 0 X X

1 1 X X

D

D

D

D

D

D

D

C

C

C

C

C

C

C

B

B

B

B

B

B

B

SOP implementation

  • 15 unique product terms if we minimize individually

C0 = A + B D + C + B' D'

C1 = C' D' + C D + B'

C2 = B + C' + D

C3 = B' D' + C D' + B C' D + B' C

C4 = B' D' + C D'

C5 = A + C' D' + B D' + B C'

C6 = A + C D' + B C' + B' C

4 input, 7 output PLA: 15 AND gates

PAL: 4 product terms per output (28 AND gates)


Better sop for pla

A

A

1 1 X 1

1 1 X 1 1 1 X X

0 1 X X

1 1 X 1

1 1 X 1 1 1 X X

0 1 X X

D

D

C

C

B

B

C2

C2

Better SOP for PLA

  • Can do better than 15 product terms

    • Share terms among outputs  only 9 unique product terms

    • Each output not necessarily minimized

  • For example:


Better sop for pla1

15 unique product terms if minimized individually

9 unique product terms if we try to share terms among outputs

Better SOP for PLA

C0 = A + BD + C + B'D'

C1 = C'D' + CD + B'

C2 = B + C' + D

C3 = B'D' + CD' + BC'D + B'C

C4 = B'D' + CD'

C5 = A + C'D' + BD' + BC'

C6 = A + CD' + BC' + B'C

C0 = BC'D + CD + B'D' + BCD' + AC1 = B'D + C'D' + CD + B'D'C2 = B'D + BC'D + C'D' + CD + BCD'C3 = BC'D + B'D + B'D' + BCD'C4 = B'D' + BCD'C5 = BC'D + C'D' + A + BCD'C6 = B'C + BC' + BCD' + A


Pla implementation

PLA implementation

ABCD

BC'

B'C

B'D

BC'D

C'D'

CD

B'D'

A

BCD'

C0 = BC'D + CD + B'D' + BCD' + AC1 = B'D + C'D' + CD + B'D'C2 = B'D + BC'D + C'D' + CD + BCD'C3 = BC'D + B'D + B'D' + BCD'C4 = B'D' + BCD'C5 = BC'D + C'D' + A + BCD'C6 = B'C + BC' + BCD' + A

C0 C1 C2 C3 C4 C5 C6 C7


Multilevel logic

Multilevel logic

  • Basic idea: Simplify logic using more than 2 gate levels

    • Time–space (speed versus gate count) tradeoff

      • Will talk about the speed issue with timing diagram

  • Two-level logic usually

    • Has smaller delays (faster circuits)

    • more gates and more wires (more circuit area)

  • Multilevel logic usually

    • Has fewer gates (smaller circuits)

    • more gate delays (slower circuits)


Example

Example

  • SOP: X = ADF + AEF + BDF + BEF + CDF + CEF + G

    • X is minimized!

    • Six 3-input ANDs; one 7-input OR; 26 wires

  • Multilevel: X = (A+B+C)(D+E)F + G

    • Factored form

    • One 3-input OR, two 2-input OR's, one 3-input AND; 11 wires


Multilevel nand nand

Level 1Level 2Level 3Level 4

C

D

F

B

A

B

C'

C

D

F

B

A

B

C'

Multilevel NAND/NAND

F = A(B+CD) + BC'

original

AND-ORnetwork

introduce bubbles

(conserve inversions)


Multilevel nor nor

Level 1Level 2Level 3Level 4

C

D

F

B

A

B

C'

C

D

F

B

A

B

C'

Multilevel NOR/NOR

F = A(B+CD) + BC'

original

AND-ORnetwork

introduce bubbles

(conserve inversions)


Generic multilevel conversion

A

A

(a)

(b)

B

B

F

F

C

C

X

X

D

D

add double bubbles at inputs

original circuit

A

(c)

(d)

A

X

B

F

C

X'

B

F

C

D'

X'

D'

distribute bubbles

some mismatches

insert inverters to fix mismatches

Generic multilevel conversion

F = ABC + BC + D = AX + X + D


Issues with multilevel design

Issues with multilevel design

  • No global definition of “optimal” multilevel circuit

    • Optimality depends on user-defined goals

  • Synthesis requires CAD-tool help

    • No simple hand methods like K-maps

    • CAD tools manipulate Boolean expressions

    • Covered in more detail in CSE467


Multilevel logic summary

Multilevel logic summary

  • Advantages over 2-level logic

    • Smaller circuits

    • Reduced fan-in

    • Less wires

  • Disadvantages wrt 2-level logic

    • More difficult design

    • Less powerful optimizing tools


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