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Evolving Peering with a New Router Architecture

Evolving Peering with a New Router Architecture. Jean-David LEHMANN-CHARLEY Compass-EOS RIPE 67, Athens j d.lehmann@Compass-EOS.com. Peering Requirements / Challenges. Availability Critical service on limited number of nodes HA hardware features Scalability Bandwidth (100G interconnects)

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Evolving Peering with a New Router Architecture

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  1. Evolving Peering with a New Router Architecture • Jean-David LEHMANN-CHARLEY • Compass-EOS • RIPE 67, Athens • jd.lehmann@Compass-EOS.com

  2. Peering Requirements / Challenges • Availability • Critical service on limited number of nodes • HA hardware features • Scalability • Bandwidth (100G interconnects) • Port density (Nx10G, 100G) • BGP scaling • FIB convergence • Dual stack IPv4/IPv6 • MP-BGP to support both AFs • RIB/FIB scaling

  3. Peering Requirements / Challenges • Stable/evolved BGP implementation • Flexible routing policy framework • 4-byte ASN support, capability negotiation route reflectors, confederations • Security • Infrastructure filtering • Accounting (Netflow v9, IPFIX) • Control plane protection • Colocation Cost control • Space • Power Consumption

  4. Lessons from the Data Center Market Virtualized Data Center Monolithic Mainframes Clustering & VirtualizationBrought Efficiency to the Data Center

  5. Evolution of Industries Networks Data Centers Can Networks Follow The Data Center Evolution?

  6. So why do we have “Mainframe-like” routers? It’s Electronics and Copper Limitations

  7. Zooming in on the challenge • Chip I/O at speeds of 100G is limited to a few centimeters • Requiring Amplification every 2/3 cm • Requiring MORE electronics • Requiring MORE cooling • Requiring MORE space

  8. Compass-EOS icPhotonics™ World First Chip-to-Chip Optical Interconnect

  9. icPhotonics™World’s First Chip-to-Chip Optical Interconnect Digital CMOS chip • 1.34Tb/s Full Duplex Bandwidth • Order of magnitude higher Chip I/O Density. 64Gb/a per mm2 • Passive optical links that stretch to Hundreds of Meters vs. Centimeters with Electronics Laser Matrix Photo Detectors Standard I/O Direct optical interface • Direct Coupling to CMOS Chip • Low energy consumption: 10pJ/bit • Dozens of Patents Covering Technology & Processes • Flexible form factor • Deployed in Production

  10. Scaling icPhotonics™ to Even Higher Capacities Over 10Tb/s ! Scale-Up Increase VCSEL Speed 8 Gb/s Per Channel Scale-Out Enlarge VCSEL Matrix 12 x 14 Today: 1.34b/s SHIPPING

  11. icPhotonics™ – Inter-Chip PhotonicsRevolutionizing Backplane Connectivity The Compass-EOS Way:icPhotonics™Passive Optical Mesh The Traditional Way:Multi-Layer Midplaneand Switching Fabric ComplexHigh CostsHigh PowerLarger Systems Limited BW/Slot SimpleLower CostsLower Power Smaller Footprint Unlimited BW/Slot

  12. Enabling a simplified routing building-block

  13. Enabling the Vision of Network Virtualization SDN ServiceData Center Simplifying the Network with Routing Building Blocks & SDN

  14. How icPhotonics plays Enabled by Compass-EOS icPhotonics™

  15. Asaf.Somekh@Compass-EOS.com

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