ELE22MIC Lecture 24

1. ELE22MIC Lecture 24 • Course Review 1 • Review Addressing Modes operation • Instruction Set Categories & instructions • Review of Assignment 1 & 2 • Assignment 3 Available • ELE22MIC MICROPROCESSORS EXAM • VENUE: THE ODEON - UNION BUILDING • DATE: 7 November 2005 • Starting At 14:00 Duration: 2:15

2. Addressing Modes • From Lecture 5: • Immediate • Direct • Extended • Indexed • Inherent • Relative

3. Immediate Addressing Mode • The data for the operation immediately follows the instruction • The # symbol must be used to select immediate addressing • Examples: • LDAA #$42 ; Load Acc.A with the value $42 -> Machine Codes: 86 42 • LDX #DEEE ; Load Index Register X with hex value DEEE -> Machine Codes CE DE EE

4. Direct Addressing Modes • Direct Addressing can access an operand located in the first 256 bytes of memory, $00..$FF • An 8-bit memory address specifies where: data is read from, or data is written to. • Examples: • LDAA $42 ; AccA = Memory[$42] • -> Machine Code 96 42 • STAA $FF ; Memory[FF] = AccA • LDX $12 ; IX = Memory[$12]..[$13]

5. Extended Addressing Modes • Extended Addressing uses 16-bit address to specify where: data is read from, or data is written to. Can be used for memory from 0..$FFFF • Examples: • LDAA $4231 ; AccA = Memory[$4321] • -> Machine Code B6 42 31 • STAA $2000 ; Memory[$2000] = AccA • LDX $1234 ; IX = Memory[$1234]..[$1235]

6. Indexed Addressing Modes (1) • Indexed addressing always uses one of two index registers X or Y. • Instruction Format: • Operation Offset, Index_Register • Offset is a positive 8-bit value (0..255) added to the contents of the index register (X or Y) • The value of the index register is not altered. • Addition is modulo 65536

7. Indexed Addressing Modes (2) • EXAMPLE: • LDAA 42, X ; AccA = Memory[42+X] • -> Machine Code A6 42 • LDAA FF, X ; AccA = Memory[255+X] • -> Machine Code A6 FF • Offset byte is considered unsigned.

8. Inherent Addressing Modes • All data for the instruction is within the CPU. • ABA ; A = A + B -> Machine code $1B • MUL ; D = A * B -> Machine code $3D • NEGA ; A = -A -> Machine code $40 • ABX ; X = X + A -> Machine code $3A • INX ; X = X + 1 -> Machine code $08 • SEC ; CarryFlag= 1 -> Machine code$0D • TAB ; B = A -> Machine code $16

9. Addressing Modes Review • Immediate, Direct, Extended, Indexed, Inherent, Relative • LDAA 4231 -> B6 42 31 • LDAA 42 -> 96 42 • LDAA #42 -> 86 42 • LDAA 42, X -> A6 42 • BRA 2020 -> 20 1E (at $2000) • ABA -> 1B • No memory to memory moves w/o register

10. Instruction Set Categories • From Lecture 6: • ARITHMETIC • BRANCH, JUMP & SUBROUTINE CALL/RETURN • COMPARE • DATA MOVEMENT • LOGICAL

11. ARITHMETIC Instructions • ADDITION, • SUBTRACTION, • TWOS COMPLEMENT (NEGATION), • DECREMENT & INCREMENT • MULTIPLY & DIVIDE • ARITHMETIC/LOGICAL SHIFT/ROTATE • BINARY CODED DECIMAL • CLEAR (bit(s) = 0) & SET (bit(s) = 1) • COMPARE & TEST • CONDITION CODE MANIPULATION • CONDITIONAL Branches • SIGNED / UN-SIGNED NUMERIC INTERPRETATION • DATA MOVEMENT Push/Pull • Load/Store Register • Transfer Registers • Exchange Registers • INTERRUPT HANDLING: • LOGICAL • LOGICAL AND • LOGICAL EXCLUSIVE OR • LOGICAL OR • ONES-COMPLEMENT (NOT) • MISCELLANEOUS

12. ADDITION • ABA A = A + B • ABX IX = IX + B • ABY IY = IY + B • ADCA A = A + M + CarryFlag • ADCB B = B + M + CarryFlag • ADDA A = A + M • ADDB B = B + M • ADDD D = D + M

13. SUBTRACTION • SBA A = A - B • SBCA A = A - M - CarryFla • SBCB B = B - M - CarryFlag • SUBA A = A - M • SUBB B = B - M • SUBD D = D - M

14. NEGATION • NEG M = -M (direct, indexed, extended) • NEGA A = -A • BEGB B = -B • TWOS COMPLEMENT • Relevent for signed numbers only, • MSB indicates sign • Each bit is inverted, then • one is added.

15. DECREMENT • DEC M = M - 1 • DECA A = A - 1 • DECB B = B - 1 • DES SP = SP - 1 • DEX IX = IX - 1

16. INCREMENT • INC M = M + 1 • INCA A = A + 1 • INCB B = B + 1 • INS SP = SP + 1 • INX IX = IX + 1 • INY IY = IY + 1

17. MULTIPLY / DIVIDE • MULTIPLY • MUL D = A * B • DIVIDE • IDIV IX = D / IX, D = D % IX • (Unsigned Integer Divide) • FDIV IX = D / IX, D = D % IX • (Unsigned fractional divide - Radix point assumed left of bit 15 of both operands)

18. Arithmetic/Logical Shift & Rotate

19. ARITHMETIC SHIFT • LEFT: (Multiply by 2) • ASL Arithmetic Shift Left (M) • ASLA Arithmetic Shift Left (A) • ASLB Arithmetic Shift Left (B) • ASLD Arithmetic Shift Left (D) • RIGHT: (Divide By 2, Sign-Extend MSBit) • ASR Arithmetic Shift Right (M) • ASRA Arithmetic Shift Right (A) • ASRB Arithmetic Shift Right (B)

20. LOGICAL SHIFT • LEFT: (Same as ASL) • LSL Logical Shift Left (M) • LSLA Logical Shift Left (A) • LSLB Logical Shift Left (B) • LSLD Logical Shift Left (D) • RIGHT: (Zero Fill MSBit) • LSR Logical Shift Right (M) • LSRA Logical Shift Right (A) • LSRB Logical Shift Right (B) • LSRD Logical Shift Right (D) • ROTATE • LEFT: (extended multiply) • ROL ROtate Left (M) • ROLA ROtate Left (A) • ROLB ROtate Left (B) • RIGHT: (extended divide) • ROR ROtate Right (M) • RORA ROtate Right (A) • RORB ROtate Right (B) • BINARY CODED DECIMAL (BCD) • DAA Decimal Adjust after Addition • Branch & Jump • BRA Branch Always • BRN Branch Never • JMP Jump to Address • JSR Jump to Subroutine • NOP No OPeration ; i.e do nothing but fetch next instruction • CLEAR (bit(s) = 0) & SET (bit(s) = 1) • CLR M = 0 • CLRA A = 0 • CLRB B = 0 • BCLR Clear Bits (M) • BSET Set Bits (M) • COMPARE & TEST • CONDITION CODE MANIPULATION • CLC CarryFlag = 0 Clear Carry Flag • CLV OVerflowFlag = 0 Clear Overflow Flag • SEC CarryFlag = 1 Set Carry Flag • SEV OVerflowFlag = 1 Set Overflow Flag • TAP CCR = A Transfer A to Condition Codes Register (CCR) • TPA A = CCR Transfer CCR to A • CONDITIONAL Branches • BEQ Branch if EQual • BNE Branch if Not Equal • BCC Branch if CarryFlag is Clear • BCS Branch if CarryFlag is Set • BRCLR Branch if bits clear • BRSET Branch if bits set • Branches for SIGNED NUMERIC INTERPRETATION • BMI ; Branch if MInus • BPL ; Branch if PLus • BVS ; Branch if oVerflow Set • BVC ; Branch if oVerflow Clear • BLT ; Branch if Less Than • BGE ; Branch if Greater-Than or Equal-to • BLE ; Branch if Less-Than or Equal-to • Branches for UN-SIGNED NUMERIC INTERPRETATION • BHI ; Branch if HIgher than • BHS ; Branch if Higher or Same • BLS ; Branch if Lower or Same • BLO ; Branch if Lower • DATA MOVEMENT • Push - Push register value onto stack • PSHA M[SP--] = A The contents of the A register is pushed onto the stack - i.e. stored into memory at the address contained in the stack pointer; then the stack pointer is decremented. • PSHB M[SP--] = B • PSHX M[SP--] = IX.LOW ; M[SP--] = IX.HIGH • PSHY M[SP--] = IY.LOW ; M[SP--] = IY.HIGH • Pull - Pull (POP) value from stack to Register • PULA ; A = M[++Sp] The stack pointer is first incremented, and then Accumulator A is popped off the stack - i.e. loaded from memory where the stack pointer is pointing. • PULB ; B = M[++SP] • PULX ; X.HIGH = M[++SP] ; X.LOW = M[++SP] • PULY ; Y.HIGH = M[++SP] ; Y.LOW = M[++SP] • Load Register • LDAA A = M • LDAB B = M • LDD D = M • LDS SP = M • LDX X = M • LDY Y = M • Store Register • Transfer Registers • TAB ; A = B • TBA ; B = A • TSX ; IX = SP + 1 • TSY ; IY = SP + 1 • TXS ; SP = IX - 1 • TXY ; SP = IY - 1 • Exchange Registers • XGDX ; D <=> IX • XGDY ; D <=> IY • INTERRUPT HANDLING: • CLI ; Clear interrupt Mask • SEI ; Set interrupt Mask • SWI ; Software Interrupt • RTI ; Return from Interrupt • WAI ; Wait for interrupt • LOGICAL • LOGICAL AND • ANDA ; A = A & M • ANDB ; B = B & M • LOGICAL EXCLUSIVE OR • EORA ; A = A ^ M • EORB ; B = B ^ M • LOGICAL OR • ORAA ; A = A | M • ORAB ; B = B | M • ONES COMPLEMENT (NOT) • COM ; M = M# • COMA ; A = A# • COMB ; B = B# • MISCELLANEOUS • STOP ; Stop clocks • TEST ; Special test mode (different meaning to 80x86)

21. ROTATE • LEFT: (extended multiply) • ROL ROtate Left (M) • ROLA ROtate Left (A) • ROLB ROtate Left (B) • RIGHT: (extended divide) • ROR ROtate Right (M) • RORA ROtate Right (A) • RORB ROtate Right (B)

22. CLEAR/BIT CLEAR/BIT SET • BYTE CLEAR: • CLR M = 0 (direct, indexed / extended) • CLRA A = 0 (Acc A) • CLRB B = 0 (Acc B) • BIT CLEAR: • BCLR Clear Bits (M) • Clears the bits that are set in the mask M, • All other bits left unchanged • BIT SET: • BSET Set Bits (M) • Sets bits that are set in the mask M • All other bits left unchanged

23. Jump (1) • JUMP address (0..$FFFF, 0..$FF, offset,X) • JMP Jump to Address • JSR Jump to Subroutine • RTS ReTurn from Subroutine • NOP No OPeration ; i.e do nothing but fetch next instruction

24. Jump (2) • JMP Jump to Address • Load the specified address, into the program counter. • Functions like GOTO in C/BASIC/PASCAL. • For memory in range $100..FFFF - • uses extended addressing • For memory in range $00..FF - • uses direct addressing • For memory in range offset, X • uses indexed addressing

25. Branch • BRANCH (-128..+127) • Branch • BRA Branch Always • BRN Branch Never • BSR Branch to SubRoutine • BSR - Same function as JSR but relative jump to subroutine i.e. must lie within +127..-128 bytes from next instruction. Saves one byte.

26. COMPARE & TEST • CONDITION CODE MANIPULATION • CLC CarryFlag = 0 CLear Carry Flag • CLV OVerflowFlag = 0 • SEC CarryFlag = 1 SEt Carry Flag • SEV OVerflowFlag = 1 • TAP CCR = A Transfer A to CCR • TPA A = CCR Transfer CCR to A • CCR = Condition Codes Register

27. CONDITIONAL BRANCHES (1) • CONDITIONAL Branches • BEQ Branch if EQual • BNE Branch if Not Equal • BCC Branch if Carry Flag is Clear • BCS Branch if Carry Flag is Set • BRCLR BRanch if bits CLeaR • BRSET BRanch if bits SET

28. CONDITIONAL BRANCHES (2) • SIGNED COMPARISON • BMI Branch if Minus • BPL Branch if PLus • BVS Branch if oVerflow Set • BVC Branch if oVerflow Clear • BGT Branch if Greater-Than > • BGE Branch if Greater-than or Equal-to >= • BLE Branch if Less-than or Equal-to <= • BLT Branch if Less Than <

29. CONDITIONAL BRANCHES (3) • SIGNED NUMBERS • Signed byte range: • -128..127 • “Byte Integer” • Signed word range: • -32768..32767 • “Word Integer”

30. CONDITIONAL BRANCHES (3) • UN-SIGNED COMPARISON • BHI Branch if HIgher than > • BHS Branch if Higher or Same >= • BLS Branch if Lower or Same <= • BLO Branch if Lower < • Unsigned byte range: 0..255 • Unsigned word range: 0..65535 (2 bytes)

31. PUSH • Push - Push register value onto stack • PSHA M[SP--] = A The contents of the A register is pushed onto the stack - i.e. stored into memory at the address contained in the stack pointer; then the stack pointer is decremented. • PSHB M[SP--] = B • PSHX M[SP--] = IX.LOW ; M[SP--] = IX.HIG • PSHY M[SP--] = IY.LOW ; M[SP--] = IY.HIGH • Pull - Pull (POP) value from stack to Register • PULA ; A = M[++Sp] The stack pointer is first incremented, and then Accumulator A is popped off the stack - i.e. loaded from memory where the stack pointer is pointing. • PULB ; B = M[++SP] • PULX ; X.HIGH = M[++SP] ; X.LOW = M[++SP] • PULY ; Y.HIGH = M[++SP] ; Y.LOW = M[++SP] • Load Register • LDAA A = M • LDAB B = M • LDD D = M • LDS SP = M • LDX X = M • LDY Y = M • Store Register • Transfer Registers • TAB ; A = B • TBA ; B = A • TSX ; IX = SP + 1 • TSY ; IY = SP + 1 • TXS ; SP = IX - 1 • TXY ; SP = IY - 1 • Exchange Registers • XGDX ; D <=> IX • XGDY ; D <=> IY • INTERRUPT HANDLING: • CLI ; Clear interrupt Mask • SEI ; Set interrupt Mask • SWI ; Software Interrupt • RTI ; Return from Interrupt • WAI ; Wait for interrupt • LOGICAL • LOGICAL AND • ANDA ; A = A & M • ANDB ; B = B & M • LOGICAL EXCLUSIVE OR • EORA ; A = A ^ M • EORB ; B = B ^ M • LOGICAL OR • ORAA ; A = A | M • ORAB ; B = B | M • ONES COMPLEMENT (NOT) • COM ; M = M# • COMA ; A = A# • COMB ; B = B# • MISCELLANEOUS • STOP ; Stop clocks • TEST ; Special test mode (different meaning to 80x86)

32. PULL • Pull - Pull (POP) value from stack to Register • PULA ; A = M[++Sp] The stack pointer is first incremented, and then Accumulator A is popped off the stack - i.e. loaded from memory where the stack pointer is pointing. • PULB ; B = M[++SP] • PULX ; X.HIGH = M[++SP] ; X.LOW = M[++SP] • PULY ; Y.HIGH = M[++SP] ; Y.LOW = M[++SP] • Load Register • LDAA A = M • LDAB B = M • LDD D = M • LDS SP = M • LDX X = M • LDY Y = M • Store Register • Transfer Registers • TAB ; A = B • TBA ; B = A • TSX ; IX = SP + 1 • TSY ; IY = SP + 1 • TXS ; SP = IX - 1 • TXY ; SP = IY - 1 • Exchange Registers • XGDX ; D <=> IX • XGDY ; D <=> IY • INTERRUPT HANDLING: • CLI ; Clear interrupt Mask • SEI ; Set interrupt Mask • SWI ; Software Interrupt • RTI ; Return from Interrupt • WAI ; Wait for interrupt • LOGICAL • LOGICAL AND • ANDA ; A = A & M • ANDB ; B = B & M • LOGICAL EXCLUSIVE OR • EORA ; A = A ^ M • EORB ; B = B ^ M • LOGICAL OR • ORAA ; A = A | M • ORAB ; B = B | M • ONES COMPLEMENT (NOT) • COM ; M = M# • COMA ; A = A# • COMB ; B = B# • MISCELLANEOUS • STOP ; Stop clocks • TEST ; Special test mode (different meaning to 80x86)

33. Load Register • LDAA A = M • LDAB B = M • LDD D = M • LDS SP = M • LDX X = M • LDY Y = M

34. Store Register • STAA M = A • STAB M = B • STS M = SP • STD M = D • STX M = IX • STY M = IY

35. Transfer Registers • TAB ; A = B • TBA ; B = A • TSX ; IX = SP + 1 • TSY ; IY = SP + 1 • TXS ; SP = IX - 1 • TXY ; SP = IY - 1 • TSX, TSY - used for setting up a stack frame for referencing parameters passed on stack.

36. Exchange Registers • Swaps 16 bit registers • XGDX ; D <=> IX • XGDY ; D <=> IY

37. INTERRUPT HANDLING: • CLI ; Clear interrupt Mask • disable hardware interrupts • SEI ; Set interrupt Mask • enable hardware interrupts • SWI ; Software Interrupt • used for system calls - eg BUFFALO • RTI ; Return from Interrupt • used at end of ISR to return • WAI ; Wait for interrupt • pushes interrupt stack values onto stack then waits for IRQ

38. LOGICAL (1) • LOGICAL AND • ANDA ; A = A & M • ANDB ; B = B & M • Each bit is ANDed with the operand • LOGICAL EXCLUSIVE OR • EORA ; A = A ^ M • EORB ; B = B ^ M • Each bit is XORed with the operand

39. LOGICAL (2) • LOGICAL OR • ORAA ; A = A | M • ORAB ; B = B | M • Each bit is ORed with the operand • ONES COMPLEMENT (NOT) • COM ; M = M# • COMA ; A = A# • COMB ; B = B# • Each bit is inverted

40. MISCELLANEOUS • STOP ; Stop clocks • TEST ; Special test mode • (different meaning to 80x86 instruction) • BINARY CODED DECIMAL (BCD) • DAA Decimal Adjust after Addition

41. Branch • BRANCH (PC + [-$80..$7F]) • Jump relative to current program counter (PC) • Used if the destination is close to the current instruction • Branch • BRA Branch Always • BRN Branch Never • BSR Branch to subroutine

42. Using Subroutines - JSR • JSR 16 bit address ($0..$FFFF, 0..$FF) • JSR Jump to Subroutine • Push next instruction address onto stack • then jump to the specified address • RTS Return from Subroutine • Pul the top item on the stack into the Instruction Pointer - effectively jumps to the address on the top of stack. This address is the value pushed by the JSR (or BSR) instruction.

43. Using Subroutines - BSR • BSR relative address (PC + [-$80 .. +$7F]) • BSR Branch to Subroutine • Push next instruction address onto stack • then branch to the specified relative address • How it works: • The program counter is incremented by 2. (as usual) • The PC of the next instruction is pushed onto the stack (so the stack contains the return address) • Then the relative displacement is added to the Program counter, and execution continues from there (i.e. within the subroutine).

44. INTERRUPTs SWI • SWI ; Software Interrupt • Pushes all user registers (not stack pointer) • The interrupt mask bit is set • this prevent furthur interrupts being serviced immediately • Fetches the Vector Address from memory location • Jumps to the vector address from memory at FFF6..FFF7

46. Stack contents - during interrupt service routine

47. INTERRUPTs RTI/WAI • RTI ; Return from Interrupt • WAI ; Wait for interrupt

48. INTERRUPT MASKING: • CLI ; CLear Interrupt Mask • Enable Interrupts on IRQ# line • SEI ; SEt Interrupt Mask • Disable Servicing of Interrupts on IRQ# line • Interrupt mask does not affect SWI (Software Interrupt) nor XIRQ.

49. Acknowledgments • Motorola M68HC11 Reference Manual • HC11 images derived from Motorola 11rm.pdf - HC11 Reference Manual