Reconfigurable FPGAs for Space – Present and Future. Rick Padovani Xilinx, Inc. MAPLD 2005. Abstract.
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The capability to implement reconfigurable digital systems based on FPGA technology is a reality today. Reconfigurability is defined in a continuum ranging from rapid design development, post-deployment hardware modifications, through to runtime reconfiguration for processing and computing. In addition, designer are increasingly looking to FPGA-based computing as performance improvements of traditional Von Neuman processors begin to level off. These topics are of increasing interest to designers of Space-based systems.
Two emerging technologies, Rad Hard by Design (RHBD), and runtime Partial Reconfiguration (PR) will dramatically increase the efficiency and reduce the cost of using reconfigurable FPGAs in Space Applications. Today’s reconfigurable FPGAs are susceptible to Single-Event Effects (SEEs) which can corrupt the configuration memory and affect the user’s design. Reconfigurable FPGAs can be made virtually immune to SEEs through the use of Triple-Module Redundancy (TMR) and configuration memory scrubbing, although these techniques bring added PCB complexity and reduce the number of available logic cells. Efforts are underway to introduce RHBD FPGAs that will be immune to SEEs. FPGAs employing RHBD configuration memory will not require TMR or configuration memory scrubbing for protection against SEEs and will offer increased reconfigurable capability for field upgrades and runtime Partial Reconfiguration (PR).
Runtime PR offers a means for changing design modules on-the-fly, while the “base” design continues to operate uninterrupted. This allows multiple design modules to time-share the same physical silicon resources, thereby reducing device resource utilization, device count, and power consumption.
Partial Reconfiguration is available today, and will become increasingly important for space-based systems where PCB footprint, mass, and power consumption are of even greater concern. This paper will review the present and future state of commercial process technology, reconfigurable FPGA architecture, FPGAs for Space, and the benefits offered by PR and RHBD.
1999 2001 2003 2005 2007 2009 2011 2013 2015 2017
Programmable “System in a Package”
Domain-optimized System Logic
Device Complexity and Performance
Compute Density of Processors
Source: UC Berkeley HERC and CPUscorecard.com
In general, the need for parallel execution is now
recognized as a requirement, as is the desire for
customizable instruction sets
Three axes of performance
To date, the only model in widespread use for supercomputing-type applications is HDL
Spectrum of Reconfiguration
Field UpgradesRapid Design Data Processing Networking Signal Processing
Configuration Memory LayerFPGA Partial Reconfiguration
PR Region A
PR Region B
PRM_B2Partial Reconfiguration Modules (PRMs)
FPGA Radiation ToleranceTID Trends vs Product/Technology
TID tolerance of Military-grade FPGAs with full production test:
*See “CMOS SCALING, DESIGN PRINCIPLES and HARDENING-BY-
DESIGN METHODOLOGIES” by Ron Lacoe, Aerospace Corp
2003 IEEE NSREC Short Course 2003
PROMApplied MitigationTMR + Scrubbing
FPGA can manage its
own configuration scrubbing!
Logic Capacity of Virtex Rad Tolerant FamiliesCurrent Virtex Families with TMR Mitigation vs. Future RHBD Families
by Design Families
Current Virtex Families
Available Logic Cells (K)
Effective Array Utilization Range
for a typical TMR Design
XQVR1000 XQR2V6000 XQR2VP70 SIRF 4V100
(Virtex) (Virtex-II) (Virtex-II pro) (Virtex-4 RHBD)
SEU Immune Reconfigurable FPGA (SIRF)
Phase-1: Design Feasibility, Test Chip and Trade Study
Phase-2: SIRF Product Development and Fabrication