Small and Fast Finite Field Multipliers for Field Programmable Gate Arrays (FPGAs)

1. Small and Fast Finite Field Multipliers for Field Programmable Gate Arrays (FPGAs) Gregory C. Ahlquist Air Force Institute of Technology Brent E. Nelson and Michael D. Rice Brigham Young University 1

2. Overview • Motivation • Challenge • Problem Statement • Background • Design Method • Results • Conclusion 2

3. Why Finite Field Multipliers on FPGAs? Fast, Flexible Hardware Applications Reed-Solomon (RS) Error Control Coding Software Defined Radios Finite Field Multipliers Cryptography Applications Dynamic Encryption Other FPGAs Other 3

4. Why Small and Fast Finite Field Multipliers? Small, Fast Finite Field Multipliers More Applications Supported Smaller, Faster Applications Application Space RS, Crypto Circuits Dominated by Finite Field Multipliers! Size FPGA Applications Speed 4

5. The Challenge • Implement Smaller, Faster FPGA-Based Finite Field Multipliers • Issues • Commercial Computer Aided Design (CAD) Tools Limited • Hand-Mapping Outperforms CAD Tools • Additional Size/Speed Gains are Possible! 5

6. The Challenge Relevant FPGA-Finite Field Multiplier Design Characteristics • FPGA Architecture • Look-Up-Tables (LUTs) • Figure-of-Merit • Algorithmic Tech-Mapping • Exclusive-Or Sum of Products (ESOPs) • Multiple-Output Equations • Pipelining Murgai, et al Sources of Challenges and Sasao,et al Sources of Opportunity Sasao, et al Various Authors 6

7. Problem Statement THE GOAL: Exploit Unique Characteristics of FPGA-Finite Field Multiplier Design Challenge To Produce Smaller and Faster Designs 7

8. Background • Finite Field Multiplication • FPGA Architectures • Logic Networks • Useful Notions and Definitions 8

9. Finite Field Multiplication Think Modulo Function! c(x) =a(x)*b(x) mod g(x) (1) Example: Let a(x) = a2x2 + a1x + a0 b(x) = b2x2 + b1x + b0 c(x) = c2x2 + c1x + c0 g(x) = x3 + x + 1 All binary coefficients! ESOP Switching Function! Challenge Re-Stated: Optimize and MapSg(x) to LUT Based FPGAs ! 9

10. FPGA Architecture Logic Blocks I/O Buffers I/O Buffers I/O Buffers I/O Buffers Interconnect • Key Limitation: Design to 4-Input LUTS Only • Ubiquitous • Finite Field Multiplier “Sweet Spot” 10

11. Logic Networks a0 b0 c0 a1 c1 b1 a2 c2 b2 Useful For Representing Switching Functions • Directed Acyclic Graph (DAG) • Primary Inputs • Primary Outputs • Internal Nodes • Input Set • Output Set • Function Key Definition: A Logic Network Is Feasible If All Internal Nodes Have Less Than 4 Inputs. 11

12. Useful Notions and Definitions V N = 4 • Evaluating Design Trade-Offs • Figure-of-Merit • Area Estimation Function • Retiming • Combinatorial to Pipeline • Pipeline to Combinatorial • Bin-Packing • Pack I items (variables) with Cost C (one) into B bins (LUTs) of Capacity N (LUT inputs) N = # of LUTs V = # of Vars Example: V = 6, N = 2 12

13. Design Method Overview Construct Sg(x) Sg(x) Partial Mapping Initial DAG Map Unmapped Terms Updated DAG Updated DAG Is DAG Feasible? Finished Yes No Bin-Pack Add New Pipe Stage 13

14. Partial Mapping and Initial DAG a0b0 a0 p0 b0 c0 p1 a1 c1 a1b1 b1 p2 c2 a2 a2b2 b2 Initial DAG • Partially Optimize and Map Sg(x) • Key Property: Terms aibj and ajbi always appear in same equations • Suggests a reasonable initial Mapping! 14

15. Mapping Unmapped Terms Most Complicated Step! • Key Idea: Use Duplicate Logic! However 15

16. Mapping Unmapped Terms AlgorithmStep #1 Create Table XM 16

17. Mapping Unmapped TermsTable XM a0b0 a1b1 a2b2 c0 c1 c2 17

18. Mapping Unmapped TermsStep #2: Pairing and Mapping a0b0 a1b1 a2b2 c0 X X c1 X c2 X • Use Table XM! Pair table XM entries such that • All columns are represented (Covered) • If outputs are even, all rows appear 0 or even times • Else one row may appear an odd number of times • This Example: Only One Pairing: ((0,0), (2,1), (0,2)) • In General: Multiple Pairings Possible • Use Figure-of-Merit to Select Best! 18

19. Updated DAG (Final Mapping) p3 a0 p0 b0 c0 a1 p1 c1 b1 p4 a2 c2 p2 b2 Where Note: Duplicate Logic DAG is Feasible DAG is Pipelined 19

20. Results • Compared Against Synplify Pro (7.0.1) • Started with Switching Function Sg(x) • Synplify produced combinatorial - retimed to pipeline. • Our method produced pipelined - retimed to combinatorial. • Register Dominated Versus Balanced • In FPGAs, Balanced always results in less area. • Functional Density • Measure of both performance and area • Smaller value is better 20

21. Pipelined Results Pipelined Finite Field Multipliers Synplify Pro (7.0.1) Our Method Sg(x) Percent Improvement LB FD reg LB reg CT FD CT 1011 6 4 4.312 8 0 43.120 4.312 34.496 20.0 10011 12 11 4.312 12 0 99.176 4.312 51.744 47.8 110001101 1110011 100101 10111111 110101001 111011 101011111 11001011 11010011 1011011 57 71 29 59 61 49 30 19 50 21 60 33 71 34 31 56 16 61 31 42 4.827 4.525 4.746 4.422 4.827 5.656 5.398 4.727 5.398 5.129 29 42 18 52 54 41 23 41 53 32 1 2 0 4 1 1 1 0 1 0 569.319 271.500 294.447 584.067 534.402 718.312 175.602 534.402 229.944 567.240 4.312 4.627 4.312 4.312 4.627 4.422 4.312 4.422 4.312 4.627 224.224 228.536 79.596 142.296 237.160 198.961 198.961 137.984 194.334 106.128 65.1 51.7 49.2 63.6 67.0 60.5 54.7 60.8 60.9 53.8 21

22. Combinatorial Results Combinatorial Finite Field Multipliers Our Method Sg(x) Synplify Pro (7.0.1) Percent Improvement CT LB FD FD CT LB 1011 6 53.137 7.591 7.591 -16.7 45.546 7 10011 12 74.528 33.3 6.210 9.316 111.790 12 18 6.350 100101 20 40.0 9.520 114.240 190.400 11.467 111011 19 18 154.805 217.870 8.601 28.9 1011011 29 11.829 27 8.812 239.537 343.041 30.2 1110011 30 11.569 28 30.0 347.070 8.673 242.949 10111111 50 682.950 39 13.659 8.195 319.621 53.2 11001011 57 12.181 39 694.317 9.136 356.294 48.7 11010011 59 12.340 728.060 9.255 39 50.4 360.945 101011111 49 50 8.231 411.570 38.8 13.719 672.231 110001101 71 13.775 446.310 978.025 8.265 54.4 54 14.204 110101001 61 50 866.444 50.8 426.120 8.522 22

23. Conclusions Small, Fast Finite Field Multipliers More Applications Supported Smaller, Faster Applications FPGA Mapping ESOPs Multiple-Outputs Pipelining Exploit Smaller, Faster Multipliers (Up to 67%!) Multiplier Switching Function Produce Automated Design Method Input 23