A survey on reconfigurable computing for signal processing applications
Download
1 / 12

A survey on Reconfigurable Computing for Signal Processing Applications - PowerPoint PPT Presentation


  • 68 Views
  • Uploaded on

A survey on Reconfigurable Computing for Signal Processing Applications. Anne Pratoomtong Spring2002. History of Reconfigurable Computing. FPGAs by Xilinx, 1986 Collection of fine grained programmable logic blocks interconnected via wires and programmable switches.

loader
I am the owner, or an agent authorized to act on behalf of the owner, of the copyrighted work described.
capcha
Download Presentation

PowerPoint Slideshow about ' A survey on Reconfigurable Computing for Signal Processing Applications' - vaughan-buck


An Image/Link below is provided (as is) to download presentation

Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author.While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server.


- - - - - - - - - - - - - - - - - - - - - - - - - - E N D - - - - - - - - - - - - - - - - - - - - - - - - - -
Presentation Transcript
A survey on reconfigurable computing for signal processing applications

A survey on Reconfigurable Computing for Signal Processing Applications

Anne Pratoomtong

Spring2002


History of reconfigurable computing
History of ApplicationsReconfigurable Computing

  • FPGAs by Xilinx, 1986

    Collection of fine grained programmable logic blocks interconnected via wires and programmable switches.

  • Programmable digital signal processors (PDSP)

    TMS32010 had a hardware multiplier and Harvard architecture with separate on-chip bus for data memory and program memory.


Reconfigurable computing for dsp
Reconfigurable computing for DSP Applications

  • Pre-Runtime Reconfigurable

  • Run-time Reconfigurable (RTR)

    -FPGAs base RTR

    -Structure Adaptive RTR


Pre runtime reconfigurable
Pre-Runtime Reconfigurable Applications

  • Computing system or device logic functionality and interconnect can be customized to suit a specific application through post-fabrication, user-defined programming

  • Hardware Platform contains a mix variety of macro module with different characteristic connected via reconfigurable communication network


Run time reconfigurable rtr
Run-time Reconfigurable (RTR) Applications

  • System logic and/or interconnect functionality can be modified during application execution

  • Useful for DSP applications whose performance and functionality depend on run-time factors such as time-varying noise, runtime environment, computation resources available, or time-varying data set


Fpgas base rtr
FPGAs Base RTR Applications

  • The adaptation is done at the hardware level using the FPGA base system.

  • Develop methodology for fast and low overhead reconfiguration.

  • Software library or driver is developed to handle reconfiguration request


Structure adaptive rtr self adaptive software
Structure Adaptive RTR : Self -Adaptive Software Applications

  • Digital signal processing system can modify its own structure (i.e. the composition of the signal flow) while it is running.

  • Software synthesis tool creates the executable version of SFG.

  • Run-time kernel schedules the computational blocks as dictated by the control graph topology and the availability of data and/or request. Each computation blocks are consider as a process which can run in UNIX-based, IBM-PC/DOS etc. platform.


Structure adaptive rtr system level synthesis
Structure Adaptive RTR:System-level synthesis Applications

  • Extend the capability of the Self-adaptive software.

  • Hardware platform is a part of system model and is chosen by the designer.

  • Construct system models of all possible aspect of adaptive computing

  • Perform synthesis based on the system models to map the application into an execution platform


Conclusion
Conclusion Applications

  • RTR system does not fully utilize the ability to change the structure of the hardware reconfigurable component such as FPGA


Conclusion1
Conclusion Applications

  • In some application, the need of RTR is gone when implementation platform consist of multiple computing hardware rather than single computing hardware. The performance factor for the 2 choices depends on communication speed VS reconfigurable overhead, area, and power constraint. In general, the single hardware implementation leads to a more power-area effective system.


Conclusion2
Conclusion Applications


Conclusion3
Conclusion Applications

  • Hardware reconfiguration for the RTR system largely occur during the synthesis phase where the real time requirement does not effect the performance. During the runtime, the reconfiguration only occurs in the form of changing the operating mode to minimized the reconfiguration overhead.


ad