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Phase 1 – Lecture – 2/25/2013. Background. Background. Design Process. Identify a problem and define solution requirements Break problem into smaller pieces Research all possible solutions Design all pieces to solution Prove functionality of each piece separately

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design process
3Design Process
  • Identify a problem and define solution requirements
  • Break problem into smaller pieces
  • Research all possible solutions
  • Design all pieces to solution
  • Prove functionality of each piece separately
  • Integrate all pieces into working unit
research
5Research
  • Determine components used for each individual stage of our Pipelined CPU
  • Transition components to be used with other team’s stages of our Pipelined CPU
    • What are Reg Files?
    • What is Pipelining?
pipelining
6Pipelining

Computer Organization and Design, 4th Ed, D. A. Patterson and J. L. Hennessey

front end
9

Front End

The United States Postal Service

research roles
10Research - Roles
  • Park Lamerton – Lead Engineer
  • Nik Marinov – Intra Team Relations
  • Taylor Foster – Team Worker
  • Kelle McCan – Wiki Specialist
  • Melissa Allee - Historian
front end1
12

Front end mimics a mailing service

Front End
  • Collect the mail.
    • Fetch instruction from memory.
  • Sort the mail.
    • Decode instruction.
    • Distribute data to desired locations.
  • Process replies.
    • Write back to destination register.
instruction fetch
13Instruction Fetch

Collecting the Mail

  • PC tells MEMORY what instruction to fetch.
  • PC controlled by two multiplexers.
  • One instruction fetched at a time.
instruction encoding
14

Types of instructions on the MIPS processor

Instruction Encoding

R-TYPE

SHAMT

RT

OPCODE

RS

RD

FUNCT

32 26 21 16 11 6 0

I-TYPE

IMMEDIATE

(offset, int, bit sequence)

RS

OPCODE

RT

32 26 21 16 0

J-TYPE

JUMP ADDRESS

OPCODE

32 26 0

instruction decode
15

Sort the mail

Instruction Decode
  • Distribute data to proper locations.
  • Sign or Zero extend immediate value.
  • Forward register data to execution.
  • Write back computed results into desired register.
register file read data
16

Sort the mail

Register File Read Data
  • Registers contain previously written or default values.
  • Mux forwards data based on the 5-bit register address.
  • All logic operations are performed on the rising edge of clock.
register file write back
17

Process replies

Register File Write Back
  • Decode write back address.
  • Wait for control bit.
  • Write data to destination register.
  • All logic operations are performed on the falling edge of clock.
execution
18

Execution

The Executives

the team
19The Team
  • Michael Bowman – Lead Engineer
  • Laly Vang – Wiki Specialist
  • Matt Goranson – Intra Team Relations
  • Darryle Parker – Intra Team Relations
  • Matthew Horton – Report Compiler
  • Austin O’Neil – Historian
exposition
21Exposition
  • Responsible for instruction execution and address calculation
  • Topics:
    • ALU
    • Branch/Jump
branch logic
23Branch Logic
  • Why?
  • What?
  • Where?
branch logic2
25Branch Logic
  • Depends on 3 signals
    • Zero
    • BNE Control
    • BEQ Control
  • PC + 4 is the default case (No branching/jumping)
jump register
26Jump Register

R-type

  • It can take you places…

.org 0x1000000

here:

lui $t0 0xdead

ori $t0 $t0 0xbeef

jr $t0

nop

jump and link register
27

R-type

Jump… and Link Register

Hey! Listen!

Go places… and remember where we were (sort of).

.org 0x1000000

here:

li $t0 joy

jalr $ra $t0

nop

done:

j done

joy:

jr $ra

jump and link register1
28Jump and Link Register
  • Logic Required
    • Jump control signal – allows a jump
    • Jump register control – allows a jump from register
    • New address (register value) – where we’re going
    • Link control signal – pass a linked address to a register
  • Resultants
    • New PC address – where we’re going
    • PC control signal – allows update of PC
    • Next instruction address (PC+4) for write back – the linked address
slide30
29Jump
  • Very much like Jump Register, only we’re jumping to an immediate
  • But we’re limited. Instructions are 32 bits with the most significant six bits being the operation code.
    • We’ve only got 26 bits to work with, but we can use up to 28.
    • First two bits 0 next 26 bits from the jump address field and upper four bits from the old PC value
  • Jump logic
    • Jump Immediate – allows an immediate jump to a new location
    • Value from register – the new address
    • Jump Control – to allow a jump
jump and link
30Jump and Link
  • Similar to JALR but uses the same address scheme used in Jump
  • Saves address for future use
  • Jump logic
    • Jump Immediate – allows an immediate jump to a new location
    • Jump Register Control Signal – allows register value to be taken
    • Value from register – the new address
    • Link Control Signal – to pass a linked address to a register
slide32
31ALU
  • Main math unit
exposition alu
32Exposition: ALU
  • “Arithmetic and Logic Unit”
  • Performs arithmetic and logical operations.
  • Does any calculations necessary to execute an instruction
encoding
33

5-bits: 4-bit encoding with extra Sub bit

12 Operations

Encoding
adder subtractor
34Adder/Subtractor

ADD

Result = Op1 + Op2

SUB

Result = Op1 - Op2

= Op1 + (!Op2 + 1)

= (Op1 +!Op2) + 1

slt sltu
35SLT/SLTU

SLT

Easy

SLTU

Similar, but a caveat

controls
40

Controls

Controlling your life, everyday.

the team1
41The Team
  • Kory Teague – Lead Engineer
  • Kyle Lawler – Wiki Specialist
  • Andres Vega – Intra Team Relations
  • Bryan Rogers – Team Worker
  • Michael Oltmanns - Historian
responsibilities
42Responsibilities
  • Manage the Control Path
    • All non-hazard control logic
  • Memory Stage
  • Writeback Stage
mem and wb
50MEM and WB
  • Provided
  • Allow for data flow
  • MemRead, MemWrite
  • LW, data first appears in MEM
    • Requires stall
    • Hazards
  • Writes to Reg File
  • MemToReg, RegWrite
hazards
51

HAZARDS

The Hazarding

team introduction
52Team Introduction
  • Spencer Hood – Lead Engineer
  • Jessie Monterroso – Wiki Specialist
  • Zach Smith
  • Max Jeter – Report Compilations
  • Evan Novotny
introduction
53Introduction
  • One down side of the pipeline is hazards
  • If hazards aren’t properly handled then the processor will behave in unexpected ways and can lower throughput
  • There are three types of hazards that will be covered in this presentation
types of hazards
54Types of Hazards
  • Data Hazards
  • Control Hazards
  • Structural Hazards
data hazards
55Data Hazards
  • RAR (Read after Read)
  • RAW (Read after Write)
  • WAR (Write after Read)
  • WAW (Write after Write)
  • RAW is the only one of the above hazards that effects the MIPS pipeline
  • Load use
example of raw hazard
56Example of RAW Hazard
  • ADD $t0, $t1, $t2
  • SUB $t3, $t0, $t4
  • Register $t0 is used in the instruction immediately after it is written to
solution for raw hazard
57Solution for RAW Hazard
  • Forwarding

http://cs-alb-pc3.massey.ac.nz/notes/59304/Image168.gif

example of load use hazard
58Example of Load use Hazard
  • lw $t0, 4($t1)
  • addiu $t2, $t0, 0x0badbeef
  • Memory is the fourth stage of the pipeline
solution for load use hazard
59Solution for Load use Hazard
  • Stall the pipeline

http://upload.wikimedia.org/wikipedia/commons/thumb/d/d0/Data_Forwarding_%28Two_Stage%29.svg/370px-Data_Forwarding_%28Two_Stage%29.svg.png

control hazards
60Control Hazards
  • Conditional Branching
    • Branch prediction
    • Assume branch is always taken
    • When its not taken flush the pipeline
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