Phase 1 lecture 2 25 2013
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Phase 1 – Lecture – 2/25/2013. Background. Background. Design Process. Identify a problem and define solution requirements Break problem into smaller pieces Research all possible solutions Design all pieces to solution Prove functionality of each piece separately

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Phase 1 lecture 2 25 2013

Phase 1 – Lecture – 2/25/2013


Background

1

Background


Background1

2

Background


Design process

3

Design Process

  • Identify a problem and define solution requirements

  • Break problem into smaller pieces

  • Research all possible solutions

  • Design all pieces to solution

  • Prove functionality of each piece separately

  • Integrate all pieces into working unit


Process

4

Process


Research

5

Research

  • Determine components used for each individual stage of our Pipelined CPU

  • Transition components to be used with other team’s stages of our Pipelined CPU

    • What are Reg Files?

    • What is Pipelining?


Pipelining

6

Pipelining

Computer Organization and Design, 4th Ed, D. A. Patterson and J. L. Hennessey


Pipelining our cpu

7

Pipelining Our CPU


Our cpu

8

Our CPU


Front end

9

Front End

The United States Postal Service


Research roles

10

Research - Roles

  • Park Lamerton – Lead Engineer

  • Nik Marinov – Intra Team Relations

  • Taylor Foster – Team Worker

  • Kelle McCan – Wiki Specialist

  • Melissa Allee - Historian


Research timeline

11

Research - Timeline


Front end1

12

Front end mimics a mailing service

Front End

  • Collect the mail.

    • Fetch instruction from memory.

  • Sort the mail.

    • Decode instruction.

    • Distribute data to desired locations.

  • Process replies.

    • Write back to destination register.


Instruction fetch

13

Instruction Fetch

Collecting the Mail

  • PC tells MEMORY what instruction to fetch.

  • PC controlled by two multiplexers.

  • One instruction fetched at a time.


Instruction encoding

14

Types of instructions on the MIPS processor

Instruction Encoding

R-TYPE

SHAMT

RT

OPCODE

RS

RD

FUNCT

32 26 21 16 11 6 0

I-TYPE

IMMEDIATE

(offset, int, bit sequence)

RS

OPCODE

RT

32 26 21 16 0

J-TYPE

JUMP ADDRESS

OPCODE

32 26 0


Instruction decode

15

Sort the mail

Instruction Decode

  • Distribute data to proper locations.

  • Sign or Zero extend immediate value.

  • Forward register data to execution.

  • Write back computed results into desired register.


Register file read data

16

Sort the mail

Register File Read Data

  • Registers contain previously written or default values.

  • Mux forwards data based on the 5-bit register address.

  • All logic operations are performed on the rising edge of clock.


Register file write back

17

Process replies

Register File Write Back

  • Decode write back address.

  • Wait for control bit.

  • Write data to destination register.

  • All logic operations are performed on the falling edge of clock.


Execution

18

Execution

The Executives


The team

19

The Team

  • Michael Bowman – Lead Engineer

  • Laly Vang – Wiki Specialist

  • Matt Goranson – Intra Team Relations

  • Darryle Parker – Intra Team Relations

  • Matthew Horton – Report Compiler

  • Austin O’Neil – Historian


Phase 1 schedule

20

Phase 1 Schedule


Exposition

21

Exposition

  • Responsible for instruction execution and address calculation

  • Topics:

    • ALU

    • Branch/Jump


Phase 1 lecture 2 25 2013

22


Branch logic

23

Branch Logic

  • Why?

  • What?

  • Where?


Branch logic1

24

Branch Logic

  • BEQ

  • BNE


Branch logic2

25

Branch Logic

  • Depends on 3 signals

    • Zero

    • BNE Control

    • BEQ Control

  • PC + 4 is the default case (No branching/jumping)


Jump register

26

Jump Register

R-type

  • It can take you places…

.org 0x1000000

here:

lui $t0 0xdead

ori $t0 $t0 0xbeef

jr $t0

nop


Jump and link register

27

R-type

Jump… and Link Register

Hey! Listen!

Go places… and remember where we were (sort of).

.org 0x1000000

here:

li $t0 joy

jalr $ra $t0

nop

done:

j done

joy:

jr $ra


Jump and link register1

28

Jump and Link Register

  • Logic Required

    • Jump control signal – allows a jump

    • Jump register control – allows a jump from register

    • New address (register value) – where we’re going

    • Link control signal – pass a linked address to a register

  • Resultants

    • New PC address – where we’re going

    • PC control signal – allows update of PC

    • Next instruction address (PC+4) for write back – the linked address


Phase 1 lecture 2 25 2013

29

Jump

  • Very much like Jump Register, only we’re jumping to an immediate

  • But we’re limited. Instructions are 32 bits with the most significant six bits being the operation code.

    • We’ve only got 26 bits to work with, but we can use up to 28.

    • First two bits 0 next 26 bits from the jump address field and upper four bits from the old PC value

  • Jump logic

    • Jump Immediate – allows an immediate jump to a new location

    • Value from register – the new address

    • Jump Control – to allow a jump


Jump and link

30

Jump and Link

  • Similar to JALR but uses the same address scheme used in Jump

  • Saves address for future use

  • Jump logic

    • Jump Immediate – allows an immediate jump to a new location

    • Jump Register Control Signal – allows register value to be taken

    • Value from register – the new address

    • Link Control Signal – to pass a linked address to a register


Phase 1 lecture 2 25 2013

31

ALU

  • Main math unit


Exposition alu

32

Exposition: ALU

  • “Arithmetic and Logic Unit”

  • Performs arithmetic and logical operations.

  • Does any calculations necessary to execute an instruction


Encoding

33

5-bits: 4-bit encoding with extra Sub bit

12 Operations

Encoding


Adder subtractor

34

Adder/Subtractor

ADD

Result = Op1 + Op2

SUB

Result = Op1 - Op2

= Op1 + (!Op2 + 1)

= (Op1 +!Op2) + 1


Slt sltu

35

SLT/SLTU

SLT

Easy

SLTU

Similar, but a caveat


Simple logic

36

Simple Logic


Logical shifts

37

Logical Shifts

SLL

SRL


Phase 1 lecture 2 25 2013

38

LUI


Mullo mulhi

39

MULLO/MULHI


Controls

40

Controls

Controlling your life, everyday.


The team1

41

The Team

  • Kory Teague – Lead Engineer

  • Kyle Lawler – Wiki Specialist

  • Andres Vega – Intra Team Relations

  • Bryan Rogers – Team Worker

  • Michael Oltmanns - Historian


Responsibilities

42

Responsibilities

  • Manage the Control Path

    • All non-hazard control logic

  • Memory Stage

  • Writeback Stage


Processor design

43

Processor Design


Control signals

44

Control Signals


Declared signals

45

Declared Signals


Signal definitions

46

Signal Definitions


Research1

X ≡ 0 on all signals except SE, where X ≡ 1

47

Research


Control unit design

48

Control Unit Design


Alucontrol unit design

49

ALUControl Unit Design


Mem and wb

50

MEM and WB

  • Provided

  • Allow for data flow

  • MemRead, MemWrite

  • LW, data first appears in MEM

    • Requires stall

    • Hazards

  • Writes to Reg File

  • MemToReg, RegWrite


Hazards

51

HAZARDS

The Hazarding


Team introduction

52

Team Introduction

  • Spencer Hood – Lead Engineer

  • Jessie Monterroso – Wiki Specialist

  • Zach Smith

  • Max Jeter – Report Compilations

  • Evan Novotny


Introduction

53

Introduction

  • One down side of the pipeline is hazards

  • If hazards aren’t properly handled then the processor will behave in unexpected ways and can lower throughput

  • There are three types of hazards that will be covered in this presentation


Types of hazards

54

Types of Hazards

  • Data Hazards

  • Control Hazards

  • Structural Hazards


Data hazards

55

Data Hazards

  • RAR (Read after Read)

  • RAW (Read after Write)

  • WAR (Write after Read)

  • WAW (Write after Write)

  • RAW is the only one of the above hazards that effects the MIPS pipeline

  • Load use


Example of raw hazard

56

Example of RAW Hazard

  • ADD $t0, $t1, $t2

  • SUB $t3, $t0, $t4

  • Register $t0 is used in the instruction immediately after it is written to


Solution for raw hazard

57

Solution for RAW Hazard

  • Forwarding

http://cs-alb-pc3.massey.ac.nz/notes/59304/Image168.gif


Example of load use hazard

58

Example of Load use Hazard

  • lw $t0, 4($t1)

  • addiu $t2, $t0, 0x0badbeef

  • Memory is the fourth stage of the pipeline


Solution for load use hazard

59

Solution for Load use Hazard

  • Stall the pipeline

http://upload.wikimedia.org/wikipedia/commons/thumb/d/d0/Data_Forwarding_%28Two_Stage%29.svg/370px-Data_Forwarding_%28Two_Stage%29.svg.png


Control hazards

60

Control Hazards

  • Conditional Branching

    • Branch prediction

    • Assume branch is always taken

    • When its not taken flush the pipeline


Phase 1 lecture 2 25 2013

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Questions

Questions?


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