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Acceleration

Acceleration. How to improve speed? At what costs?. T=Nq * CPI * Cycletime. Nq, Number of instructions CPI, Cycles Per Instruction Cycletime. Single Cycle Design. CPI = 1 Cycletime = Long (Longest path). Multiple Cycle. 1 < CPI < S Cycletime = Factor 1/S. Pipelined design.

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Acceleration

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  1. Acceleration • How to improve speed? • At what costs?

  2. T=Nq * CPI * Cycletime • Nq, Number of instructions • CPI, Cycles Per Instruction • Cycletime

  3. Single Cycle Design • CPI = 1 • Cycletime = Long (Longest path)

  4. Multiple Cycle • 1 < CPI < S • Cycletime = Factor 1/S

  5. Pipelined design • CPI = 1, (Constant) • Cycletime = Factor 1/S

  6. “THROUGHPUT” • The total amount of work done in a given time

  7. INSTRUCTION MEMORY STAGE (IM) Zeroext. Branch logic 0 A ALU 4 B + 31 + Sgn/Ze extend INSTRUCTION MEMORY

  8. INSTRUCTION DECODE STAGE (DE) Zeroext. Branch logic 0 A ALU 4 B + 31 + Sgn/Ze extend

  9. INSTRUCTION EXECUTE STAGE (EX) Zeroext. Branch logic 0 A ALU 4 B + 31 + Sgn/Ze extend

  10. DATA MEMORY STAGE (DM) Zeroext. Branch logic 0 A ALU 4 B + 31 + Sgn/Ze extend DATA MEMORY

  11. WRITEBACK STAGE (WB) Zeroext. Branch logic 0 A ALU 4 B + 31 + Sgn/Ze extend

  12. Pipeline • 5 stages, (IM, DE, EX, DM, WB) • Writeback NOT in critical path • Cut critical path by 4

  13. WRITEBACK STAGE (WB) Zeroext. CAN READ/WRITE THE SAME REG! Branch logic 0 A ALU 4 B + 31 + Sgn/Ze extend

  14. Single Cycle Reg IM DM Reg Reg IM DM Reg

  15. Single Cycle Reg IM DM Reg Reg IM DM Reg

  16. 4 Stage Pipe Reg IM DM Reg Reg IM DM Reg Reg IM DM Reg Reg IM DM Reg

  17. A Program 0x30 sub $6 $0 $1 0x34 add $7 $0 $1 0x38 ori $2 $0 0xABCD 0x3C sw $5 4($0) $1 holds value 0x05

  18. 4 Stage Pipe Reg • 0x30 sub $6 $0 $1 IM DM Reg • 0x34 add $7 $0 $1 Reg IM DM Reg • 0x38 ori $2 $0 0xABCD Reg IM DM Reg • 0x3C sw $5 4($0) Reg IM DM Reg

  19. Step 1 Reg • 0x30 sub $6 $0 $1 IM DM Reg • 0x34 add $7 $0 $1 Reg IM DM Reg • 0x38 ori $2 $0 0xABCD Reg IM DM Reg • 0x3C sw $5 4($0) Reg IM DM Reg

  20. Step 2 Reg • 0x30 sub $6 $0 $1 IM DM Reg • 0x34 add $7 $0 $1 Reg IM DM Reg • 0x38 ori $2 $0 0xABCD Reg IM DM Reg • 0x3C sw $5 4($0) Reg IM DM Reg

  21. Step 3 Reg • 0x30 sub $6 $0 $1 IM DM Reg • 0x34 add $7 $0 $1 Reg IM DM Reg • 0x38 ori $2 $0 0xABCD Reg IM DM Reg • 0x3C sw $5 4($0) Reg IM DM Reg

  22. Step 4 Reg • 0x30 sub $6 $0 $1 IM DM Reg • 0x34 add $7 $0 $1 Reg IM DM Reg • 0x38 ori $2 $0 0xABCD Reg IM DM Reg • 0x3C sw $5 4($0) Reg IM DM Reg

  23. Step 5 Reg • 0x30 sub $6 $0 $1 IM DM Reg • 0x34 add $7 $0 $1 Reg IM DM Reg • 0x38 ori $2 $0 0xABCD Reg IM DM Reg • 0x3C sw $5 4($0) Reg IM DM Reg

  24. Zeroext. Branch logic 0 A ALU 4 B + 31 + Sgn/Ze extend • > 0x30 sub $6 $0 $1 • 0x34 add $7 $0 $1 • 0x38 ori $2 $0 0xABCD • 0x3C sw $5 4($0)

  25. Zeroext. Branch logic 0 A ALU 4 B + 31 + Sgn/Ze extend • 0x30 sub $6 $0 $1 • > 0x34 add $7 $0 $1 • 0x38 ori $2 $0 0xABCD • 0x3C sw $5 4($0)

  26. Zeroext. Branch logic 0 A ALU 4 B + 31 + Sgn/Ze extend • 0x30 sub $6 $0 $1 • 0x34 add $7 $0 $1 • > 0x38 ori $2 $0 0xABCD • 0x3C sw $5 4($0)

  27. Zeroext. Branch logic 0 A ALU 4 B + 31 + Sgn/Ze extend • 0x30 sub $6 $0 $1 • 0x34 add $7 $0 $1 • 0x38 ori $2 $0 0xABCD • > 0x3C sw $5 4($0)

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