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CS 2204 Spring 2007

CS 2204 Spring 2007. Experiment 4 Lab 8. Experiment 4 Lab 8 Outline Presentation Digital product development overview Using Digital Product Development The high-level design of the term project The operation diagram , major operations and blocks Ppm blocks 2 and 3

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CS 2204 Spring 2007

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  1. CS 2204 Spring 2007 Experiment 4 Lab 8

  2. Experiment 4 Lab 8 Outline • Presentation • Digital product development overview • Using Digital Product Development • The high-level design of the term project • The operation diagram, major operations and blocks • Ppm blocks 2 and 3 • Digital systems • Individual work • Experiment 4 • Develop a BCD up counter (using class notes) • No new handout CS 2204 Spring 2007

  3. Presentation • Developing a Digital Product • CS2204 sets out to develop a prototype • A prototype chip • A prototype PCB • If everything goes well and the product is not obsolete, it is mass produced • Mass produce the prototype chip • Whoever wants to use the chip must develop a new PCB • Mass produce the prototype PCB CS 2204 Spring 2007

  4. Developing a digital product • A new chip • Which gates/FFs and how many is determined by • The application (major operations) • Available components of the technology chosen • Besides speed, cost, power, etc. : product goals • A new PCB • Which chips and how many is determined by • The application (major operations) • Available chips of the technology chosen • Besides speed, cost, power, etc. : product goals CS 2204 Spring 2007

  5. Developing a new chip TEST : applying input combinations, test vectors, and simulating 1)Development Cycle on Computers During testing you will see modifying hardware to minimize it is possible. Do that after you correct logic and timing errors. Then, test again to see if your minimization has logic/timing errors Design TEST MODIFY Major error : Redesign Major error : Redesign or terminate the project due to TTM Mount : FPGAs are mounted on bread/boards, wired and programmed 2)Development Cycle with FPGA chips Test : apply test vectors to FPGAs Mount Test Modify Modify : either FPGA mounting/wiring is changed or a simple design change is made on computers, simulated, then FPGAs are programmed and tested Major error : Redesign or terminate the project due to TTM 3)Development Cycle on prototype chip Fabricate chip by sending a GDSII file to a fabrication facility : tape out Fabricate Test Apply test vectors to the chip CS 2204 Spring 2007

  6. Try to use registers, counters, shift registers even if it is a simplesequential circuit • Development Cycle on Computers • DESIGN • Input/Output Relationship • A simple circuit • Obtain the truth table of the combinational circuit with less than 5 inputs then move on to Implementation (2) • Obtain the state diagram of the sequential circuit with less than 5 FFs then move on to Implementation (2) • A complex circuit • Obtain the operationtable or the operationdiagram ►Try to implement it • If it cannot be implemented immediately in (2) ► Partition it • Implementation • TEST • MODIFY CS 2204 Spring 2007

  7. Development Cycle on Computers CS 2204 Spring 2007

  8. Designing a Complex Block • Partition it into pieces based on major operations • Besides the design goals and the technology • One block for each major operation • These major operations are often • Additions, MUXings, comparisons, decodings, encodings, DeMuxing, registering, counting, etc. • These operations are already implemented by available components/chips : • ADDers, Multiplexers, Comparators, Decoders, Encoders, DeMuxes, Registers, Counters, shift registers, etc. • This happens frequently for real-life applications CS 2204 Spring 2007

  9. An UnusualMajor Operation (an unusualblock) • Trying to implement a block • If it has < 11 inputs implement it by using programmable components • Memory components • ROMs, RAMs • Otherwise (complex or too many inputs) • Break it up or • Repartition one level up, or • Two levels up, or,… • All the way up (redesign !?) • Eventually, the resulting operations will be additions, comparisons, multiplexing, decoding, etc. CS 2204 Spring 2007

  10. Designing a New Chip • DESIGN • Input/Output relationship • A simple block Combinational circuit Sequential circuit • A circuit with less than 5 inputs • Obtain a truth table • Obtain circuit expressions • A circuit with less than 5 FFs • Obtain a state diagram • Obtain circuit expressions Move on to the Implementation step, (2) CS 2204 Spring 2007

  11. Designing a New Chip • DESIGN • Input/Output relationship • A complex block • Obtain the operation table/diagram • Try to implement it (Step 2) • If impossible, partition the block based on Application (major operations) : a subblock for each major operation Design goals : speed, cost, power, size,… ►Speed, cost, power,… depend on the technology Available components : components of the technology CS 2204 Spring 2007

  12. CS2204 • Designing a New Chip • DESIGN • Implement each circuit • One or more Xilinx Design Blocks, XDBs or Xilinx non-programmablemacros (not gates and FFs) implement the circuit ? A few gates and FFs here and there ? • If yes, draw the schematic and move to the TEST step • One or more Programmable Xilinx macros implement the circuit ? A few gates and FFs here and there ? • If yes, draw the schematic, program the macros and move to the TEST step CS 2204 Spring 2007

  13. CS2204 • Designing a New Chip • DESIGN • Implement each circuit • Simple enough to be designed quickly using Switching Theory (less than 5 inputs or less than 5 FFs) so a few gates and/or FFs needed ? • If yes, draw the schematic and move to the TEST step • The circuit can be licensed ? • If yes, borrow it, place it and move to the TEST step • If no to all the above questions, go back to step 1(b) to partition it further or repartition one level up, two levels up,,, or, all the way up CS 2204 Spring 2007

  14. Designing a New Chip • TEST • Test (sub)blocks separately • Functional and timing simulations by applying test vectors • Pick the righttest vectors and the rightorder of them • Note down these combinations and output values to use them during later testing steps • Combine (sub)blocks one at a time CS 2204 Spring 2007

  15. Designing a New Chip • MODIFY • A simple change • Minimize the circuit after you think your circuit does not have logic and timing errors • After the minimization, test the circuit to make sure the minimization does not introduce logic and timing errors CS 2204 Spring 2007

  16. Development Cycle on Computers Development Cycle with FPGA chips • Xilinx Project Development Steps • Develop the schematic • DESIGN the schematic • Design blocks, (sub)blocks • Place the components and wires • Do integrity TESTs • TEST the schematic via functional simulations • MODIFY the schematic to correct an error • Do a Xilinx IMPLEMENTATION • It maps the components to the CLBs of the chip • Do timing simulations to TEST the schematic • It generates the bit file • Download the bit file to the FPGA and test the design on the board • It programs the chip What are these components ? CS 2204 Spring 2007

  17. Use these as much as possible • CS2204 components • Available components for a new chip Xilinx components Labs Generic components Lectures, homework, exams Flip-flops Gates Flip-flops Popular digital circuits Gates Popular digital circuits ADDer Comparator Multiplexer DeMux Decoder Encoder ALU Counter Register … AND OR NOT NAND NOR … D JK T SR … ADDer Comparator Multiplexer DeMux Decoder Encoder ALU Counter Register … AND OR NOT NAND NOR … D JK To save time, space, power. weight,… CS 2204 Spring 2007

  18. a NOT AND b 1 inverter 2 2-input AND gates 1 2-input OR gate OR a AND c Total : 4 gates used y(a, b, c) =a.b + a.c • Implementing a Combinational Circuit on a NewChip • By using generic components that are AND, OR, NOT,… • The 2-to-1 MUX Which components ? CS 2204 Spring 2007

  19. 2 inverters 5 2-input AND gates 1 5-input OR gate Total : 8 gates used 2-bit Unsigned Binary Comparator From Handout 5 • Implementing a Combinational Circuit on a NewChip • By using generic components that are AND, OR, NOT,… Which components ? CS 2204 Spring 2007

  20. 1 inverter 4 2-input AND gates 6 3-input AND gates 1 4-input AND gate 4 2-input OR gates 2 3-input OR gates 3J-K FFs Total : 21 components used • Implementing a Sequential Circuit on a NewChip • By using generic components that are D, J-K, AND, OR, NOT,… • The sequence detector from Handout 10 Which components ? CS 2204 Spring 2007

  21. Lab design Use Xilinx macros as much as possible Try not to use these components • CS2204 Components • Available components for a new chip Xilinx components Labs Generic components Lectures, homework, exams Gates Flip-flops Popular digital circuits Gates Flip-flops Popular digital circuits AND OR NOT NAND NOR… D T JK ADDer Comparator Multiplexer DeMux Decoder Encoder ALU Counter Register… AND OR NOT NAND NOR… D JK T SR ADDer Comparator Multiplexer DeMux Decoder Encoder ALU Counter Register… CS 2204 Spring 2007

  22. 1 inverter 2 2-input AND gates 1 2-input OR gate Total : 4 gates used a NOT AND b OR a AND c y(a, b, c) =a.b + a.c • Implementing a Combinational Circuit on a New Chip • By using Xilinx components that are AND, OR, NOT,… • The 2-to-1 MUX Which components ? CS 2204 Spring 2007

  23. a NOT Do not design your own 2-to-1 MUX AND b OR a AND c y(a, b, c) =a.b + a.c • Implementing a Combinational Circuit on a New Chip • By using Xilinx components that are AND, OR, NOT,… • The 2-to-1 MUX Use them Xilinx already has 2-to-1 MUXes CS 2204 Spring 2007

  24. 1 Xilinx M2_1 MUX Total : 1 component used a NOT AND b OR a AND c y(a, b, c) =a.b + a.c • Implementing a Combinational Circuit on a New Chip • The 2-to-1 MUX • Xilinx already has 2-to-1 MUX macros • M2_1 Which components ? CS 2204 Spring 2007

  25. 2 inverters 5 2-input AND gates 1 5-input OR gate Total : 8 gates used • Implementing a Combinational Circuit on a New Chip • By using Xilinx components that are AND, OR, NOT,… Which components ? 2-bit Unsigned Binary Comparator From Handout 5 CS 2204 Spring 2007

  26. Do not design your own Comparator • Implementing a Combinational Circuit on a New Chip • By using Xilinx components that are AND, OR, NOT,… • 2-bit Unsigned Binary Comparator Use them Xilinx already has Comparators You need an extraOR gate besides the comparator CS 2204 Spring 2007

  27. 1 Xilinx 74_L85 Comparator 1 Xilinx 2-input OR gate Total : 2 components used • Implementing a Combinational Circuit on a New Chip • 2-bit Unsigned Binary Comparator • By using Xilinx comparators Which components ? CS 2204 Spring 2007

  28. 1 inverter 4 2-input AND gates 6 3-input AND gates 1 4-input AND gate 4 2-input OR gates 2 3-input OR gates 3 positive-edge triggered J-K FFs Total : 21 components used • Implementing a Sequential Circuit on a New Chip • By using Xilinx components that are D, J-K, AND, OR, NOT,… • The sequence detector from Handout 10 Which components ? CS 2204 Spring 2007

  29. We have to design our own sequence detector • Implementing a Combinational Circuit on a New Chip • By using Xilinx components that are D, J-K, AND, OR, NOT,… • The sequence detector from Handout 10 Xilinx does not have this sequence detector The design with 21 components isimplemented CS 2204 Spring 2007

  30. Xilinx FFs, Registers, Counters • Many do not have direct set and direct clear inputs • To avoid cases where both are active • They have either • A direct set input • Or • A direct clear input CS 2204 Spring 2007

  31. Xilinx FFs, Registers, Counters • Direct set and direct clear inputs • Asynchronous • As we studied in class • If the direct input is active, it affects the output immediately • The name of the FF, register, counter has a • “C” near the end if it is the direct clear input ►FDC : a D FF with an asynchronous direct clear input • “P” near the end if it is the direct set (preset) input ►FDP : a D FF with an asynchronous direct set input CS 2204 Spring 2007

  32. Xilinx FFs, Registers, Counters • Direct set and direct clear inputs • Synchronous • If the direct input is active, it affect the output when there is the active clock edge • The name of the FF, register, counter has an • “R” near the end if it is the direct clear input ►FDR : a D FF with a synchronous direct clear input • “S” near the end if it is the direct clear input ►FDS : a D FF with a synchronous set input CS 2204 Spring 2007

  33. Xilinx FFs, Registers, Counters • Some of them have an additional input • Clock Enable (CE) • The name of the FF, register, counter ends with an “E” • It controls the clock input • If it is 1, the clock input gets the clock signal ► It can be clocked (stored) • If it is 0, the clock input gets 0 ► It cannot be clocked (cannot be stored) • FDCE : A D FF with an asynchronous direct clear input and a clock enable input CS 2204 Spring 2007

  34. Xilinx FFs, Registers, Counters • Clock Enable (CE) • FDCE : A D FF with an asynchronous direct clear input and a clock enable input CS 2204 Spring 2007

  35. a D Q y0 Storey0 C Clock CLR Reset • Xilinx FFs, Registers, Counters • Clock Enable (CE) • The clock enable is often connected the “Store” signal CE is equivalent to a y0 Storey0 Clock Reset CS 2204 Spring 2007

  36. The Ppm Term Project • The black-box view • A large number of FFs are used ! • We need to partition the Ppm based on major operations • We have to obtain the operation diagram CS 2204 Spring 2007

  37. LD6-LD8 on the FPGA board show the current state Machine play block Points Calculation block Human play block Input/Output Block Play check block The Ppm operation diagram CS 2204 Spring 2007

  38. The Ppm Term Project Partitioning • We have observed the following major operations • Interfacing to the input/output devices • Handling human player’s play • Controlling display operations based on game rules • Calculating new player points • Determining the machine player play • Hint for general partitioning • If you cannot figure out major operations, partition one major operation at a time CS 2204 Spring 2007

  39. A Digital System • The Ppm Term Project Partitioning • Any other major operation ? • Control (time) the operations • All other operations CS 2204 Spring 2007

  40. Digital Systems • A digital systemperformsmicrooperations • A digital systemconsists of digital circuits • A digital system consists of • A data unit (datapath) • It performs microoperations • A control unit • It controls the datapath CS 2204 Spring 2007

  41. Digital Systems • This first partitioning of a digital system is universal • A microprocessor is a digital system • A computer is a collection of digital systems CS 2204 Spring 2007

  42. Digital Systems • The data unit has registers, ALUs and buses to perform microoperations • Registers keep (store) data (operands and results) • Arithmetic Logic Units (ALUs) perform additions, subtractions, multiplications, ANDS, ORs, etc. • Buses interconnect registers and ALUs CS 2204 Spring 2007

  43. Digital Systems • The data unit is highly regular • Pieces of hardware repeated many times • 1-bit MUX repeated 32 times for a 32-bit MUX • 4-bit ADDer repeated 8 times for a 32-bit ADDer • It is easier to design, test, modify, manufacture, upgrade, service, maintainregular hardware CS 2204 Spring 2007

  44. Digital Systems • The control unit determines the sequence of microoperations based on status signals • The control unit goes through steps (states) • In each state, it enables the microoperations of that state to happen in the data unit based on the status signals • Microoperations must start at the right time with correct inputs and end at the right time with correct outputs • Glitches, gate delays must be accounted for CS 2204 Spring 2007

  45. core core core core partially core non-core • The Ppm Term Project • Ppm is a digital system ! • The Ppm term project partitioning • First partitioning of the digital system • Control Unit • Data Unit • Second partitioning (Data Unit partitioning) • Interfacing to the input/output devices • Handling human player’s play • Controlling display operations based on game rules • Calculating new player points • Determining the machine player play CS 2204 Spring 2007

  46. The Ppm Digital System Partitioning M1 M2 M3 CS 2204 Spring 2007

  47. Macro 1, M1 Macro 2, M2 • The Ppm Data Unit • Experiment 5 afterall circuits are moved to their appropriate places CS 2204 Spring 2007

  48. Macro 3, M3 • The Ppm Data Unit • Experiment 6 CS 2204 Spring 2007

  49. 64 34 Block 2 • The Ppm Data Unit • Block 2, Input/Output Block • It controls input/output devices on the FPGA board and generates timing signals • Three major operations • Controls Input/Output Devices • I/O Buffer Subblock • Display Subblock • Generates timing signals for the digital system • Timing Subblock CS 2204 Spring 2007

  50. 64 34 Block 2 • The Ppm Data Unit • Block 2, Input/Output Block CS 2204 Spring 2007

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