Janusz Rajski Nilanjan Mukherjee Mentor Graphics Corporation

1. Embedded Test Embedded Test for for Low-Cost Manufacturing Low-Cost Manufacturing Janusz Rajski Nilanjan Mukherjee Mentor Graphics Corporation

2. Presenters and authors Presenters: Janusz Rajski Nilanjan Mukherjee Mentor Graphics Corporation janusz_rajski@mentor.com Co-author: Jerzy Tyszer Poznan Univ. of Technology

3. Tutorial ground rules • Definition: Embedded Test refers to design-for-testability techniques where testing is accomplished entirely or partially through on-chip hardware. • Disclaimer: This tutorial is not intended to endorse or discredit any commercial technology or product.

4. Audience Everybody interested in state-of-the-art embedded test technology, to reduce the cost of manufacturing test In particular: • Designers of complex integrated circuits • IP core providers and integrators • Test engineers • EDA tools developers • EDA tools users • Researchers • Project managers

5. Tutorial objectives To present: • Compelling reasons for ET adoption • Common barriers for ET adoption • State-of-the-art ET fundamentals and practice • Architectures for logic and memory BIST • Embedded deterministic techniques • At-speed ET • multiple-clock domain designs • multi-frequency designs • Tools for BIST synthesis automation • Application examples and case studies

6. Outline • Introduction • Embedded stimuli generators • Compactors of test responses • Logic BIST • Deterministic forms of embedded test • Embedded at-speed test • Comparison of scan/ATPG, logic BIST and embedded forms of deterministic test • BIST schemes for embedded memory arrays • Summary of embedded test

7. Introduction Introduction

8. Design characteristics CPU core DSP core IP core ASIC ASIC Memory Memory ASIC IP core I / 0 Memory Analog Memory Memory ASIC PLL

9. System architecture Microprocessors, DSP cores Buses, peripherals, memory ASIC portion Structures: Logic, memory, analog Multiple embedded memories: DRAM, Flash, CAM Analog and mixed signal: PLLs, clock recovery Field programmable logic RF cores: wireless receivers IP cores and reusable blocks available from multiple vendors Design efficiency achieved by hierarchical core-based design style System on Chip characteristics CPU core DSP core IP core ASIC ASIC Memory Memory ASIC IP core I / 0 Memory Analog Memory Memory ASIC PLL

10. New defects • Geometries shrink at 30% every three years • Defect sizes do not shrink in proportion • Increase of wiring levels from 6 to 9 • Interconnect delays dominate • Gate delays reduced • Bridging faults

11. Sematech S-121 “Test Method Evaluation –Key Findings & Conclusions” Objective: • Evaluate various test methodologies • Large sample size • Extensive data collection & analysis [Sematech, 1998]

12. Sematech S-121 • Device 116K equivalent gates • 0.45 µm L effective (0.8 µm drawn) • 50 MHz operating speed • 249 signal I/Os • 3 metal levels • Full LSSD Scan plus JTAG boundary scan • 8 Chains, 5,280 master/slave LSSD latches (10,560 total latches) • Sample size 20,000 units • Test methods: • Stuck-at faults, Functional tests, Transition delay faults & IDDQ

13. Sematech S-121 IDDQ1463 13 7 8 FUNC6 FUNC SAF6 1 1251 1 36 0 52 Delay 14 34 IDDQ • Package test results (pre Burn-in) SAF - 99.5% coverage (8300 patterns) FUNC - 52% SAF coverage (532K cycles) Delay - 90% Transition coverage (15232 patterns) IDDQ - >96% pseudo SAF coverage(195 patterns)

14. S-121 Conclusions • All test methods detected unique defects • Near 100% SAF coverage missed many defects • Large defect coverage overlap between SAF & Delay • SAF are a subset of Transition faults • IDDQ threshold setting significantly affects yield • 98% of the IDDQ fails survived burn-in • Many (bridging) defects detected only by IDDQ • But diminishing IDDQ effectiveness in DSM • Some Functional tests are still required • Opportunity to optimize test coverage levels & capital

15. Process Shrinks vs. Defect Types Unknown BridgeM1-2 Via break Bridge M2 Bridge M4 Break trans Bridge Poly M2 Bridge M3 Bridge M1-3 Bridge poly M1 Bridge M3-4 Open Poly Open Contact Bridge M1 Unknown Br Break M3 Bridge Poly M2 Break M2 Bridge M3-4 Break M1 Bridge Poly M4 Bridge Poly Defect Pareto 350 nm 350 nm Process 5 million Transistors Al 4-5 Levels W Plugs Oxide Dielectric A Transistor

16. Defect distribution change with process Process Shrinks vs. Defect Types Defect Pareto 100 nm 100 nm Process -- 250 million transistors Unknown ? Cu (8 Levels) Low-K Dielectric Cu Plugs A Transistor

17. Defects vs. Fault Coverage Increasing defect populations causing more V , Temp, & freq sensitive device fails DD • Wired “AND” & “OR” models are not sufficient • Speed limiting defects • Frequency of bridging defects is increasing • Need to drive ATE & modeling requirements from the defects to be detected • Will drive need for more scan vectors Bridge Defect Observed Resistance .18 um .25 um Test chip FA results 1 10 100 1000 K-Ohms [M. Rodgers , et. al. DAC 2000]

18. Quality requirements shipment Escapes 1 - p Faults detected p Y 1 - Y

19. Quality requirements Escapes = (1 - Y)(1 - p) Yield = 0.9 Yield = 0.1 p

20. Fault models VDD • Stuck-at-0 and stuck-at-1 • Transitions • Path delay • Multiple detects

21. Very high test quality • Very high fault coverage • Wide range of fault models • stuck-at • transition • path delay • at-speed testing • multiple detects • bridging • defect based • cross-talk effects • ... fading IDDQ Coverage Escapes

22. High-performance MPU/ASIC gate count Gate count ITRS Roadmap 2001

23. Scan chains • The pattern count for transition faults may reach 20,000

24. Scan test Primary outputs Scan input channels Scan output channels Primary inputs ATE

25. ATE cost b [ K$ ] m [ $ ] p High performance ASIC / MPU 250 - 400 2700 - 6000 512 DFT tester 100 - 350 150 - 650 512 - 2500 Low performance Microcontroller 200 - 350 1200 - 2500 256 - 1024 Tester cost = b + S m p b - base cost (zero pins) m - incremental cost per pin p - number of pins Test cost can be $0.05/second

26. Volume of scan test data Scan cells Scan chains ... Patterns Test cycles =

27. Scan test time Patterns Frequency ... Scan cells  Test time = Scan chains

28. Scan test cost Gate count 10M 500,000 Scan cells Scan chains 32 15,625 Cells per scan Padding ratio 1.4 21,875 Longest scan chain Scan patterns 20K 437.5M Cycles Shift frequency 20 MHz 21.9s Scan test time Vector memory 64MV 6 Passes Reload penalty 2s 12.0s Reload time Insertions 4 87.5s Time pre device Tester rate 0.05$ 4.4$ Cost per device More

29. High-performance MPU/ASIC Required ATE memory Gigabits/channel 32 channels 20,000 patterns

30. High-performance MPU/ASIC Scan test time seconds 100 MHz scan shift

31. ATE accuracy vs. device speed • Tester accuracy will improve from 200 ps to 175 ps by 2012 • Clock period will decrease to 330 ps • Margin of error for ATE approaches 50% clock period Device period ATE accuracy Accuracy required

32. Requirements for Embedded Test • Increasing device complexity, operating speed, and new fault models stress conventional scan based test: • Exploding volume of test data • Increasing scan test time, and • Escalating scan test cost • Embedded Test is required to: • Generate most of the test data on-chip • Compacting test responses on-chip, and • Providing on-chip control for at-speed test

33. Very low cost 10X 10X • Dramatically reduced volume of test data (10-100X) • Dramatically reduced scan test time (10-400X) 16 scan chains 5k vectors 2s handler/index time 1 test 10MHz scan shift ATE Memory [Mvectors] 2M gates Scan/ATPG Scan test time[s]

34. Long term scalability 100X increase in 10 years! Volume in conventional DFT years

35. Radical compression is required! • Immediate 5-10X compression • Compression ahead of volume for 10 years Compression factor Volume in conventional DFT years

36. Radical compression is required Compression should be ahead of Moore’s law for 10 years! Compression factor Volume in conventional DFT Compressed volume years