R. Meshkin, A. Saberkari*, and M. Niaboli

1. A Novel 2.4 GHz CMOS Class-E Power Amplifier with Efficient Power Control for Wireless Communications R. Meshkin, A. Saberkari*, and M. Niaboli Department of Electrical Engineering University of Guilan Rasht, Iran International Conference on Electronics, Circuits and Systems Athens, Greece Dec. 2010

2. Outline • Introduction • Baseline Class-E Power Amplifier Topology • Expressions and Relationships • Conventional Power Control Techniques • Design Procedure • Circuit Characterization • Conclusion 2 Introduction Baseline Top. Expressions Conv. Power Design Proc. Characterize Conclusion

3. Introduction • Power Amplifier (PA) • The Last Building Block of a Transmitter Chain in Transceiver ICs • The Most Power Consuming Block in any RF Transmitter • Linear and Nonlinear PAs • Linearity is in conflict with Efficiency. • Constant Envelope Modulation Scheme => Nonlinear PAs • Class-E PA => Better Choice in Terms of • Circuit Simplicity • High Efficiency • Good Performance at Higher Frequencies 3 Introduction Baseline Top. Expressions Conv. Power Design Proc. Characterize Conclusion Conclusion

4. Baseline Class-E PA Topology Soft Switching Properties: Classical Class-E Power Amplifier Topology 4 Introduction Baseline Top. Expressions Conv. Power Design Proc. Characterize Conclusion

5. Expressions and Relationships Load Network Components Value: Ropt = Optimum Load Resistance Pout = Desired Output Power ω = Resonant Frequency Vdd = Supply Voltage Efficiency: Pdc = Supply Power Pout = Output Power Pin = Input Power 5 Introduction Baseline Top. Expressions Conv. Power Design Proc. Characterize Conclusion

6. Conventional Power Control Techniques • Power Control with Variable Supply Voltage 6 Introduction Introduction Baseline Top. Expressions Conv. Power Design Proc. Characterize Conclusion

7. Conventional Power Control Techniques • Power Control with Parallel Amplification 7 Introduction Introduction Baseline Top. Expressions Conv. Power Design Proc. Characterize Conclusion

8. Conventional Power Control Techniques • Power Control with Array of Switches with Different Sizes 8 Introduction Introduction Baseline Top. Expressions Conv. Power Design Proc. Characterize Conclusion

9. Design Procedure • Two-Stage Configuration (Driver Stage and Power Stage) • Cascode Transistor: • High Isolation from the Input to the Output • Protect Switching Transistors (Breakdown) • Class-E Driver Stage => More Efficiency & Closer to Optimum Driving Signal • Matching Network => As Much as Possible Power from Source to the Load Proposed Class-E Power Amplifier 9 Introduction Introduction Baseline Top. Expressions Conv. Power Design Proc. Characterize Conclusion

10. Design Procedure • Output Power Control: • Changing the Size of the Switching Devices, And • Suitable External Shunt Capacitors Calculated for Each Steps of Output Power • Small Size Controlling Switches => located in the Gate Terminal due to the Low Current of Gate Proposed Structure for Output Power Control 10 Introduction Introduction Baseline Top. Expressions Conv. Power Design Proc. Characterize Conclusion

11. Design Procedure Circuit Elements Value 11 Introduction Introduction Baseline Top. Expressions Conv. Power Design Proc. Characterize Conclusion

12. Design Procedure Chip Layout 1381 µm*1234 µm 12 Introduction Introduction Baseline Top. Expressions Conv. Power Design Proc. Characterize Conclusion

13. Circuit Characterization Drain Current and Voltage Waveforms of Cascode Transistor M4 13 Introduction Introduction Baseline Top. Expressions Conv. Power Design Proc. Characterize Conclusion

14. Circuit Characterization Output Power and PAE Versus Supply Voltage 14 Introduction Introduction Baseline Top. Expressions Conv. Power Design Proc. Characterize Conclusion

15. Circuit Characterization Output Power and PAE as a Function of Frequency 15 Introduction Introduction Baseline Top. Expressions Conv. Power Design Proc. Characterize Conclusion

16. Circuit Characterization Output spectrum 16 Introduction Introduction Baseline Top. Expressions Conv. Power Design Proc. Characterize Conclusion

17. Circuit Characterization PAE Values for Each Output Power Step 17 Introduction Introduction Baseline Top. Expressions Conv. Power Design Proc. Characterize Conclusion

18. Circuit Characterization Performances in Comparison with Previous Works [1] V. R. Vathulya, T. Sowlati and D. Leenaerts, 2001. [2] R. Brama, L. Larcher, A. Mazzanti and F. Svelto, 2007. [3] H. Fouad, A.H. Zekry and K. Fawzy, 2009. [4] S.A.Z, Murad, R.K. Pokharel, H. Kanaya and K. Yoshida, 2010. 18 Introduction Introduction Baseline Top. Expressions Conv. Power Design Proc. Characterize Conclusion

19. Circuit Characterization Comparison of PAE Drop in Different Output power Control Method [1] A. Sirvani, D. K. Su, B. A. Wooley, 2002. [2] M. M. Hella and M. Ismail,2002. [3] C. Wei, L.Wei and H. Shizhen, 2009. 19 Introduction Introduction Baseline Top. Expressions Conv. Power Design Proc. Characterize Conclusion

20. Conclusion • Reviewed Concepts of Classical Class-E Power Amplifiers • Presented Topological Modifications that Improve PAE and Circuit Integration Capability • Presented New Efficiently Output Power Control Technique Based on the Array of Switches and Capacitors 20 Introduction Introduction Baseline Top. Expressions Conv. Power Design Proc. Characterize Conclusion