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Peter Bannon VP of Architecture and Verification September 20, 2007

Announcing PWRficient Processors from PA Semi, the Most Power Efficient, High Performance Processors Available. Peter Bannon VP of Architecture and Verification September 20, 2007. The Escalating Power Problem. Shrinking device geometries provides Faster gates Increased density BUT

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Peter Bannon VP of Architecture and Verification September 20, 2007

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  1. Announcing PWRficient Processors from PA Semi, the Most Power Efficient, High Performance Processors Available Peter Bannon VP of Architecture and Verification September 20, 2007

  2. The Escalating Power Problem • Shrinking device geometries provides • Faster gates • Increased density BUT • Moore’s Law means more power Power Density CapacityGap Area/Gate EXCESSIVE POWER DISSIPATION LIMITS USABLE GATE CAPACITY 250nm 180nm 130nm 90nm 65nm 45nm Process Technology

  3. Choosing Power Over Ultimate Performance 80 82 84 86 88 90 92 96 94 98 100 • Look for the exponential opportunities in power/performance • Give up some performance for substantial power decrease 120 Old design point 100 80 Watts 60 40 New design point 20 0 P e r f o r m a n c e

  4. Design Choices for Low Power • Design choices at several levels favor low power • CMOS process target • Circuit design style and sizing • Micro-architecture features • Integration • Saves interface power • Management • Voltage/frequency scaling • Multiple power planes for optimal voltage selection per region • Clock gating to reduce power of idle circuits • Active and pre-charge standby modes in DRAM array • PCIe power saving modes • Nap and Sleep modes for CPU

  5. Fine-Grained Clock Gating Reduces Dynamic Power 80 70 Coarse-Grained Clock Gating 60 50 Worst Case Normal Operation % of Flops Clocked 40 30 20 Time 10

  6. PWRficient PA6T-1682M Block Diagram 2MB L2 Cache DDR2Controller DDR2Controller 64KB I-Cache 64KB I-Cache 64KBD-Cache 64KBD-Cache PA6T 2GHz Core PA6T 2GHz Core CONEXIUM™ Interchange TTM* Power Control Bridge DMA Offload Engines I/O Cache System Control PTM† Interrupt/GPIO ENVOI™ Intelligent I/O Octal PCI Express Dual 10GbE XAUI Quad GbESGMII SMBus (3) ConfigurableSERDES (24) UART (2) Boot Bus *Transaction trace memory †Peripheral trace memory

  7. Voltage/Frequency Scaling • Multiple power planes for maximum control • VID regulators for cores, SoC • Ability to scale both Vdd and frequency on demand results in highly optimized total power PA6T-1682M VID_CP0 6 PA6T Core VRM VDD_CP0 VID_CP1 6 VRM PA6T Core VDD_CP1 VID_SoC SoC VRM VDD_SoC *PA6T-1682M-FCN nap power may be higher

  8. Summary – The Green Computing Advantage • PWRficient processors set the bar for ultimate energy conservation at full performance • Lowest total energy for a computation or transaction • PWRficient processors are designed to reduce system power • Optional use of power standby mode in DDR2 memories • Only minimal performance compromises to meet power-efficiency goals • Significant operating-cost savings for cluster-based computing • Power conservation a key initiative from architectural concept though design

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