Study of Gate Line Edge Roughness Effects in Short Channel MOSFET

1. Study of Gate Line Edge Roughness Effects in Short Channel MOSFET SFR Workshop May 24, 2001 Shiying Xiong, J. Bokor UC Berkeley Qi Xiang, Philip Fisher at al. STG of AMD 2001 GOAL: Simulations for AMD device designs at 100nm, 70 nm, and 50 nm gate length, including effect of isolation roughness by 9/30/2001.

2. Motivation • This aims to quantify poly gate LER of the most advanced devices, and to model and investigate its effects. • Several possible LER effects has been simulated: • Increase on leakage and driving current • Variation of Vt • Effect on lateral diffusion and doping profile • An efficient description of LER from direct measurement of poly lines in advanced MOSFET has not been established • Substantial experimental data of devices with different LER must to be obtained to make a meaningful comparison with simulation results.

3. LER Measurement and Characterization SEM Poly LER Measurement Multi-box measurement on each poly line and 64 Scans in each box Max resolution: x:~0.8nm y:~3nm SEM current scan over line One scan x y

4. LER Measurement and Characterization Line edges are extracted by processing SEM current data x 1 2 3 4 y Unit: nm Typical poly line edges: (List from left to right) 1.Top left edge 2.Top right edge 3.Bottom left edge 4.Bottom Right edge

5. LER Measurement and Characterization y LER Characterization yi • Average Line width Scan #i • Width Variation Range • Maximum Edge Deviation from the Mean Left edge position Right edge position • Edge RMS • Width RMS:

6. LER Measurement and Characterization • Distribution of line width (MOSFET gate length ) subtracted the mean Fit function Cut 3-tail Gaussian U:Unit step function • LER Frequency properties FFT of edge waveform Power spectral density Power Spectral Density Correlation Function Correlation length *Observed line RMS value was reduced ~ 10% if filtering off LER period small than Lc

7. LER Experiments with AMD • Characterize LER on AMD wafer and develop ways to vary LER • We have developed methods to measure and characterize LER • AMD Results so far has not given reliable increase of LER • Need to work harder to increase LER for the study purpose • Simulate LER effect on AMD device using our method • AMD fabricates devices with different LER values • Comparison experimental data with simulation results

8. Simulation of LER Effect on AMD 50nm Technology Estimation of 3D long period LER device current from 2D Simulation 1.Fit leakage and driving current of 2D devices with different gate length 2.Get the current from the following equation 3. Comparison on devices with different LER from simulation

9. Conclusion • Line width RMS:1.5nm~4.5nm, Line Edge RMS: 1nm~3.5nm RMS does not scale with line width, Maximum edge deviation ~3. • Lc is generally greater than 25nm, the power of high frequency (wavelength <Lc) line edge variation is small, so HF LER is insignificant. • The prospective 50nm technology is insensitive the typical LER (Lc> 25nm, RMS_W 1.5~4.5nm) produced in process. • We need to produce LER with 4-6nm RMS to test our model • Milestones • Wafers processed at AMD finished with varying, and well-characterized LER by 9/30/2002 (This will likely be completed by 12/31/2001). • Device characterization on AMD wafers completed and data analyzed by 9/30/2003 (This will also be significantly accelerated)