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MORPHEUS project

Application design flow for the MORPHEUS heterogeneous dynamically reconfigurable platform Philippe BONNOT - THALES. MORPHEUS project. EU FP6 IST project 02 7342 Started 1st January 2006 Duration 3 years Goals : a reconfigurable architecture chip and associated toolset

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MORPHEUS project

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  1. Application design flow for the MORPHEUS heterogeneous dynamically reconfigurable platform Philippe BONNOT - THALES CASTNESS’07 workshop – Rome – 2007-01-15

  2. MORPHEUS project • EU FP6 IST project 02 7342 • Started 1st January 2006 • Duration 3 years • Goals : a reconfigurable architecture chip and associated toolset • improving computing density, flexibility (reconfiguration time) and time-to-market • Partners are: • THALES, THOMSON, ALCATEL-LUCENT, THALES Optronics, INTRACOM, ST, PACT, M2000, ACE, CRITICALBLUE • CEA, Universities of KARLSRUHE, DELFT, Bretagne Occ. , BOLOGNA, BRAUNSCHWEIG, CHEMNITZ, ARTTIC application code --------- f(.) --------- Associated toolset configuration bitstreams SW code CPU RU 1 RU 2 RU 3 programming communication CASTNESS’07 workshop – Rome – 2007-01-15

  3. Contents • Introduction • MORPHEUS execution model • MORPHEUS programming model • MORPHEUS toolset • Conclusion and perspectives CASTNESS’07 workshop – Rome – 2007-01-15

  4. MORPHEUS architecture Memories General-purpose processor Config. manager Interconnections Reconfigurable units • Coarse-grain : PACT XPP • Data flow algorithm • Huge computational demand • Medium-grained : PicoGA • Reconf. array of 4-bit oriented ALU • Target instruction level parallelism • Fine grain : eFPGA • Arbitrary logic CASTNESS’07 workshop – Rome – 2007-01-15

  5. Data Flow view Master AMBA AHB/APB + DMA Ext. DDR On-chip SRAM XPP HRE PicoGA HRE M2000 HREs ARM + OS IO periph. CM NOC + DNA Reconfiguration AMBA AHB + DMA On-chip reconfiguration RAM IO pads A data stream lives only during the life of a configuration Streams are under the control of HRE HRE are under the control of ARM (see control flow) for exec and config (and of CM for config) CASTNESS’07 workshop – Rome – 2007-01-15

  6. Execution Control Flow view Master AMBA AHB/APB + DMA Ext. DDR On-chip SRAM XPP HRE PicoGA HRE M2000 HREs IO periph. ARM + OS CM NOC + DNA Reconfiguration AMBA AHB + DMA On-chip reconfiguration RAM IO pads CASTNESS’07 workshop – Rome – 2007-01-15

  7. Configuration Flow view Master AMBA AHB/APB + DMA Ext. DDR IO periph. On-chipSRAM XPP HRE PicoGA HRE M2000 HREs ARM + OS CM NOC + DNA Reconfiguration AMBA AHB + DMA On-chip reconfiguration RAM IO pads CASTNESS’07 workshop – Rome – 2007-01-15

  8. Reconfiguration Control Flow view Master AMBA AHB/APB + DMA Ext. DDR On-chipSRAM XPP HRE PicoGA HRE M2000 HREs ARM + OS IOperiph. CM NOC + DNA Reconfiguration AMBA AHB + DMA On-chip reconfiguration RAM IO pads CASTNESS’07 workshop – Rome – 2007-01-15

  9. Contents • Introduction • MORPHEUS execution model • MORPHEUS programming model • MORPHEUS toolset • Conclusion and perspectives CASTNESS’07 workshop – Rome – 2007-01-15

  10. The application description: What programmer must do • C programming application at global level (sequences of tasks, etc) • with manual annotations to identify « HW » accelerated tasks and their synchronisation (parallel execution) • Detailing accelerated tasks • may generally be complex data-streaming processing functions that requiring data-parallelism techniques to be described and mapped • A graphical tool is proposed for that. • Engineers who usually design such systems should easily handle it. • However, the task must be split in sub-tasks easily interconnected with the proposed tool. • Sub-tasks have to be described in C. • A direct path is available when: • the accelerated task is not complex • optimisation is not expected CASTNESS’07 workshop – Rome – 2007-01-15

  11. Design Flow view Sequential C-based description of the application Graphical parallel + Ckernels description of accelerated function DMA/DNA parameters compilation-time scheduling of accelerated functions setting and execution Configuration (bitstream, …) Master AMBA AHB/APB + DMA IO periph. ARM+ OS DDR controller On-chip SRAM XPP HRE PicoGA HRE M2000 HREs CM Run-time scheduling of the configuration Run-time scheduling of the application NOC + DNA Reconfiguration AMBA AHB + DMA CASTNESS’07 workshop – Rome – 2007-01-15

  12. WP2 toolset Graphical parallel + Ckernels description of accelerated function Sequential C-based description of the application Formal verification MOLEN paradigm and compiler Sequential C-based description of the application (compilation-time scheduling of accelerated functions setting and execution) - Information on accelerated function implementations - DMA/DNA parameters ECOS-based dynamic reconfiguration control Run-time scheduling of the application Accelerated function synthesis (including memory to memory communication aspects) Configuration manager Communication mechanisms (DNA, DMA, DDR controller) Reconfigurable Units (M2000 blocks, XPP, PicoGA) Configuration (bitstream, …) CASTNESS’07 workshop – Rome – 2007-01-15

  13. Contents • Introduction • MORPHEUS execution model • MORPHEUS programming model • MORPHEUS toolset • Conclusion and perspectives CASTNESS’07 workshop – Rome – 2007-01-15

  14. WP2 toolset Graphical parallel + Ckernels description of accelerated function Sequential C-based description of the application Formal verification MOLEN paradigm and compiler Sequential C-based description of the application (compilation-time scheduling of accelerated functions setting and execution) - Information on accelerated function implementations - DMA/DNA parameters ECOS-based dynamic reconfiguration control Run-time scheduling of the application Accelerated function synthesis (including memory to memory communication aspects) Configuration manager Communication mechanisms (DNA, DMA, DDR controller) Reconfigurable Units (M2000 blocks, XPP, PicoGA) Configuration (bitstream, …) CASTNESS’07 workshop – Rome – 2007-01-15

  15. MOLEN paradigm and compiler • Made by the university of Delft and ACE company • An extension of the instruction set for the reconfigurable processing elements with : • configuration • parameter passing • execution instructions C with MOLEN annotations Expansion to MOLEN instructions Optimized placement of configuration instructions ARM assembly with MOLEN abstraction library CASTNESS’07 workshop – Rome – 2007-01-15

  16. MOLEN • Example: • C code: res = alpha(param1, param2); HW movtx XR1 ← param1 movtx XR2 ← param2 set <address_alpha_set> exec <address_alpha_exec> movfx res ← XR3 Send param. HW reconfiguration HW execution Return result CASTNESS’07 workshop – Rome – 2007-01-15

  17. MOLEN • C Source Program Annotations • MOLEN_FUNCTION id • declares the next function to correspond with PE task id • MOLEN_PARALLEL on/off • Starts/ends scope for parallel tasks execution • MOLEN_CONFLICT id1 id2 • Declares configuration conflict for tasks with id1 and id2 • MOLEN Instructions • SET (id) Configure PE for task id • MOVTX (id,val) Move value to task id • EXEC (id) Execute task id • BREAK Wait for all executing tasks • MOVFX (id,reg) Move data from task to reg • RELEASE (id) Release configuration id CASTNESS’07 workshop – Rome – 2007-01-15

  18. WP2 toolset Graphical parallel + Ckernels description of accelerated function Sequential C-based description of the application Formal verification MOLEN paradigm and compiler Sequential C-based description of the application (compilation-time scheduling of accelerated functions setting and execution) - Information on accelerated function implementations - DMA/DNA parameters ECOS-based dynamic reconfiguration control Run-time scheduling of the application Accelerated function synthesis (including memory to memory communication aspects) Configuration manager Communication mechanisms (DNA, DMA, DDR controller) Reconfigurable Units (M2000 blocks, XPP, PicoGA) Configuration (bitstream, …) CASTNESS’07 workshop – Rome – 2007-01-15

  19. Dynamic reconfiguration RTOS structure • eCos extension made by university of Karlsruhe CASTNESS’07 workshop – Rome – 2007-01-15

  20. Retargetable compilation Compiled application binary code Reconfiguration and execution system call RTOS Reconfiguration directives Dynamic reconfiguration HW status Configuration Manager Reconfiguration control Reconfiguration and execution control HW status HW status Reconfigurable units Spatial design Dynamic reconfiguration RTOS relationships • The RTOS performs: • Priority calculation • Tasks execution status management • Resource request to the Configuration Manager for fine dynamic scheduling • Allocation decision (on the various reconfigurable units) (only in the second phase of the project) • The Configuration Manager performs: • Configuration priority management • Configuration cache management • Prefetch prediction CASTNESS’07 workshop – Rome – 2007-01-15

  21. WP2 toolset Graphical parallel + Ckernels description of accelerated function Sequential C-based description of the application Formal verification MOLEN paradigm and compiler Sequential C-based description of the application (compilation-time scheduling of accelerated functions setting and execution) - Information on accelerated function implementations - DMA/DNA parameters ECOS-based dynamic reconfiguration control Run-time scheduling of the application Accelerated function synthesis (including memory to memory communication aspects) Configuration manager Communication mechanisms (DNA, DMA, DDR controller) Reconfigurable Units (M2000 blocks, XPP, PicoGA) Configuration (bitstream, …) CASTNESS’07 workshop – Rome – 2007-01-15

  22. Applications in SPEAR DE • mostly regular data streaming applications • captured as acyclic graphs of tasks • each task represented by its way to (linearly) access data from/to its input/output arrays, and as a nest of loops • SPEAR DE does not participate to creating the code within a task • SPEAR DE helps the user to select and implement a mapping of the application on the computing architecture CASTNESS’07 workshop – Rome – 2007-01-15

  23. SPATIAL DESIGN: framework architecture • Joint works of university of Bretagne Occidentale, Critical Blue and THALES company SPEAR DE • Application capture and system optimizations SPEAR sub-function (ANSI C subset) C files Cascade CriticalBlue • CDFG generation global CDFG CDFG Data flow of the process MADEO UBO • Technology mapping Bitstream CASTNESS’07 workshop – Rome – 2007-01-15

  24. Fusion MOtoM MtoOtherSeg MOtoM Mtom F MtoOtherSeg G mtoM Do 4 times Mtom mtoM F G M0 M0 M M M M M M m m m m m m CPU CPU CPU CPU CPU CPU Mapping _ Fusion of tasks Fusion reduces memory needs CASTNESS’07 workshop – Rome – 2007-01-15

  25. Design on reconfigurable units HRE HRE C F C F F F F F C C C Buffers Buffers NOC, AMBA • Synthesis of subtasks from C code • Automatic generation of interconnections and control logic CASTNESS’07 workshop – Rome – 2007-01-15

  26. MADEO: framework architecture • Behavioral & physical synthesis • Open framework Global CDFG (from SPEAR) Subtasks CDFG (from Cascade) Global and subtasks CDFG generation CDFG HLL Archi. 1 : M2000 MADEO : behavioral & physical synthesis compilation synthesis Archi. 2 : XPP Archi. 3 : PicoGA CDFG LL rewriting e.g. NML EDIF e.g. Griffy-C CASTNESS’07 workshop – Rome – 2007-01-15

  27. Contents • Introduction • MORPHEUS execution model • MORPHEUS programming model • MORPHEUS toolset • Conclusion and perspectives CASTNESS’07 workshop – Rome – 2007-01-15

  28. Conclusion and perspectives • A reconfigurable heterogeneous architecture is in development • Associated toolset based on C language, composed of 3 modules: • Retargetable compiler based on MOLEN paradigm • Reconfiguration control added to eCos OS • Accelerated function synthesis abstracts the architecture heterogeneity • Developments of application test cases in progress (Work Package 5) • A comprehensive toolset : • allows application developers to fully exploit MORPHEUS architecture • reduced time-to-market, improving flexibility • Second phase of the project: • Parallel extensions to MOLEN instruction set • Dynamic reconfiguration control • Function synthesis optimizations CASTNESS’07 workshop – Rome – 2007-01-15

  29. Application programming design flow for the MORPHEUS heterogeneous dynamically reconfigurable platform Philippe BONNOT - THALES CASTNESS’07 workshop – Rome – 2007-01-15

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