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Ch 6 Interrupt

제 41 강 : Interrupt(I). Ch 6 Interrupt. CPU & Interrupt. Instr. fetch Instr. decode Execution Read data Write Back. PC←PC+4. Interrupt request bit. Interrupt v.s. Exception. CPU.  illegal address  illegal opcode  divide by zero. Exception. enable, disable

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Ch 6 Interrupt

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  1. 제41강 : Interrupt(I) Ch 6 Interrupt

  2. CPU & Interrupt

  3. Instr. fetch Instr. decode Execution Read data Write Back PC←PC+4 Interrupt request bit Interrupt v.s. Exception CPU  illegal address  illegal opcode  divide by zero Exception enable, disable CPU PC ← address of interrupt handler Save register

  4. interrupts v.s. exceptions

  5. Many I/O devices – Interrupt Controller ` CPU Instr. fetch Instr. decode Execution Read data Write Back PC←PC+4 PC ← interrupt handler addr Save register interrupt request zero Interrupt Controller set

  6. Interrupt Controller

  7. IRQ Lines ISR (In Service Register) IMR (Interrupt Mask Register) IRR (Interrupt Request Register) Priority Register vector INTR ACK PIC(Programmable Interrupt Controller) • Many IRQ signals simultaneously • IMR: • If not masked  process IRQ • IRR: • Hold all requested IRQ’s until • they are eventually processed • Priority register: • Selects highest priority IRQ line • ISR • IRQ currently in service • Encode IRQ line # to vector # • Send interrupt signal to CPU • Waits for ack from CPU (PIC & device controller is blocked in the meantime)

  8. Ack • PIC assigns vector number per each IRQ line • Both PIC & device controller remain blocked until Ack from CPU (Bovet p. 122) • Kernel must send Ack quickly to release PIC & device controller from blocked state as soon as possible (maximize I/O throughput) • When CPU sends Ack, PIC & device go back to work. PIC can issue further interrupts.

  9. PIC History(Master/Slave PIC) CPU • XT CPU had only one INTR line • Each PIC had only 8 IRQ lines • XT had only one PIC • Many more I/O devices appears • Connect 2nd PIC (slave PIC) to 1st PIC • Master/Slave PIC • Upward compatible INTR Pin Master PIC INTR Pin Slave PIC IRQ p. 112 Bovet

  10. Many IRQ lines per PIC Many IRQ lines per PIC Mask (Enable/Disable) each IRQ line PIC is blocked after INTR Ack from CPU releases this PIC ` CPU Interrupt line (IRQn) Instr. fetch Instr. decode Execution Read data Write Back Interrupt line (IRQm) . . . Interrupt line (IRQ1) PC←PC+4 PC ← interrupt handler addr Save register VECTOR PIC zero INTR INTR set vector number is assigned per IRQ line

  11. Many devices per IRQ line ` Many devices per IRQ line Each device has status register CPU can access device status register CPU Instr. fetch Instr. decode Execution Read data Write Back Interrupt line (IRQn) Interrupt line (IRQm) PC←PC+4 . . . Interrupt line (IRQ1) PC ← interrupt handler addr Save register VECTOR zero PIC INTR INTR set

  12. Interrupt Handlingin Multiprocessor

  13. CPU #0 CPU #1 Local APIC Local APIC Timer Timer bus multi APIC IRQ from I/O devices Local & multi-APIC • Local APIC • one per each CPU in SMP (CPU local) • Timer interrupt • All local APICs are connected to (external) APIC • APIC (Advanced PIC) or multi-APIC • for multiprocessor • When a device raises IRQ, • multi-APIC selects a CPU, • delivers signal to corresponding local APIC, • which in turn interrupts CPU

  14. SMP (Symmetric Multiprocessing) CPU 0 CPU 1 CPU 2 CPU 3 Which CPU should receive this IRQm signal? APIC signal from IRQm . . . Timer Interrupt line (IRQ0) Interrupt line (IRQ1) Interrupt line (IRQk) Interrupt line (IRQm)

  15. IRQ distribution architecture • Message distribution method depends on processor • The P6 family and Pentium processors • pass messages through serial APIC bus • APIC bus arbitration • The Pentium 4 and Intel Xeon processors • pass messages through system bus • system bus arbitration (Ref) Intel Architecture Software Developer’s Manual

  16. IRQ distribution algorithm • IRQ distribution in two ways • static distribution • dynamic distribution • Static distribution • use static table (Redirection Table) • Dynamic distribution • use process priority • arbitration if same priority

  17. Dynamic IRQ distribution algorithm • Deliver IRQ to CPU running lowest priority process • Tie?  Arbitration algorithm • each processor maintains a counter (for process) • Deliver IRQ to CPU with Maximum counter value • counter  0 if IRQ is delivered (selected CPU) • counter++ if IRQ is not delivered (rest of the CPU’s)

  18. Asymmetric Multiprocessing - Only the master CPU can run OS kernel (1) slave asks master to run system call function (2) master queues all system call requests (3) master executes sys call one by one (4) I/O data are transferred from disk to shared memory Master CPU Shared Memory CPU #1 CPU #2 PC=100 PC=3000 hwp PIC Local Memory email OS Kernel ppt All I/O Devices kernel code user code

  19. Data Structure for Interrupt Handling

  20. Interrupt line (IRQm) Interrupt line (IRQn) . . . PIC Information about each IRQ line IRQ_DISABLED - interrupt not allowed (masked or not) IRQ_WAITING - (interrupt allowed but) interrupt not been raised IRQ_PENDING - (interrupt raised and Ack’ed). but notserviced by kernel yet IRQ_INPROGRESS – kernel is executing ISR Each IRQ line IRQm line Which PIC? Interrupt service routines (ISR)  device specific operations

  21. Interrupt line (IRQm) Interrupt line (IRQn) . . . PIC Flags describing status of IRQ line irq_desc[] [0] [1] [2] Which PIC? Interrupt service routines (ISR) irqaction irqaction irqaction multiple devices can share a single IRQ  device specific operations each irqaction corresponds to a specific device lock it, since many CPU’s access this data concurrently

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