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June 2013

June 2013. Enabling easy creation of HW reconfiguration scenarios for system level pre-silicon simulation Erez Bilgory Alex Goryachev Ronny Morad Tali Rabetti IBM Research – Haifa. Enabling easy creation of HW reconfiguration scenarios for system level pre-silicon simulation.

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June 2013

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  1. June 2013 Enabling easy creation of HW reconfiguration scenarios for system level pre-silicon simulationErez Bilgory Alex Goryachev Ronny Morad Tali RabettiIBM Research – Haifa

  2. Enabling easy creation of HW reconfiguration scenarios for system level pre-silicon simulation Background: System-level simulation Memory Processor Core#1 Processor Core#2 Processor Core#N • Pre-silicon, system-level RTL simulation: • Many cores (possibly multithreaded) • Many I/O devices, bridges, HW accelerators, message-passing components • All components run in parallel • Only RTL, no real SW in the simulated system … System bus HW accelerator unit Memory controller Message passing unit IO bridge I/O bus I/O BFM#1 I/O BFM#2

  3. Enabling easy creation of HW reconfiguration scenarios for system level pre-silicon simulation Background: Test generator Abstract test case (High level test description) Concrete test cases (including instruction stream for each processor core) System-level test generator

  4. Enabling easy creation of HW reconfiguration scenarios for system level pre-silicon simulation Background: Test generator Core 1 Core 2 System-level test generator Memory write Memory Read Memory write IO rd Mix 10 instructions of types: 50%: 25%: 25%: Send message to core 1 Memory write Memory access Send message to core 2 IO Rd IO Rd/Wr Memory read IO Wr Send message Abstract test case Concrete test cases

  5. E0 E1 E2 Enabling easy creation of HW reconfiguration scenarios for system level pre-silicon simulation Background: Message passing component Output Input FIFO 0 FIFO 0 Message Passing Unit Processor Core#4 FIFO 1 FIFO 1 connection Table FIFO 2 FIFO 2 FIFO 3 FIFO 3 FIFO 4 FIFO 4 (3) Read data (1) Write data Processor Core#1 Processor Core#3 (2) Initiate message transmission Processor Core#2

  6. E0 E1 E2 Enabling easy creation of HW reconfiguration scenarios for system level pre-silicon simulation Background: Message passing component Output Input FIFO 0 FIFO 0 Message Passing Unit Processor Core#4 FIFO 1 FIFO 1 connection Table FIFO 2 FIFO 2 FIFO 3 FIFO 3 FIFO 4 FIFO 4 (3) Read data (1) Write data Reconfigure entry Processor Core#1 Processor Core#3 (2) Initiate message transmission Processor Core#2

  7. Actual runtime of each operation is unknown before simulation, and can change from simulation to simulation Core 1 Core 2 Core 1 Core 2 Use E1 Random Use E1 Random Random Reconfigure E1 Reconfigure E1 Random Runtime Use E2 Random Random Reconfigure E1 Reconfigure E2 Reconfigure E2 Random Use E2 Use E1 Use E1 Reconfigure E1 Random Enabling easy creation of HW reconfiguration scenarios for system level pre-silicon simulation The reconfiguration challenge: Shared connection table entry reconfiguration Mix 10 instructions of types: 34%: 33%: 33%: Random Use entry Reconfigure entry

  8. Enabling easy creation of HW reconfiguration scenarios for system level pre-silicon simulation The reconfiguration challenge Core 1 Core 2 Use E1 Random Reconfigure E1 Random Use E2 The arrowed operations need to be synced Random Reconfigure E1 Reconfigure E2 Random Use E1

  9. Enabling easy creation of HW reconfiguration scenarios for system level pre-silicon simulation The reconfiguration challenge Core 1 Core 2 Poll: Wait until a known value is written to a semaphore address before operation Use E1 Random Signal Poll Reconfigure E1 Random Signal Use E2 Random Signal Poll Signal: Write a known value to a semaphore address after operation Poll Reconfigure E1 Reconfigure E2 Signal Poll Random Use E1

  10. Core 1 Core 2 Use entry 1 Signal semaphore 1 Random instructions Poll semaphore 1 Use entry 1 Poll semaphore 2 Use entry 2 Poll semaphore 3 Reconfigure entry 3 Signal semaphore 3 Use entry 2 Random instructions Poll semaphore 1 Reconfigure entry 1 Signal semaphore 1 Reconfigure entry 2 Signal semaphore 2 Use entry 3 Signal semaphore 3 Random instructions Poll semaphore 3 Use entry 3 Enabling easy creation of HW reconfiguration scenarios for system level pre-silicon simulation Directed test, complete with needed synchronization operation The reconfiguration challenge • Is this scenario correct? • Does it have the needed synchronization operations? • Does it have deadlocks? • Lose the test generator’s power! • Only one test scenario

  11. Enabling easy creation of HW reconfiguration scenarios for system level pre-silicon simulation Our solution: Automatic synchronization Addition Template Transactions: thread, entry, use/Reconfigure Test generator tracker Semaphore address and value to poll, if needed Test cases Core 1 Core 2 The output of the tracker is a set of synchronization operations needed to preserve the intended ordering of specific transactions with respect to each other Other transactions remain unordered random Use E1 Reconfigure E1 random random Use E2 Reconfigure E2 Reconfigure E1 Use E1 random

  12. Enabling easy creation of HW reconfiguration scenarios for system level pre-silicon simulation Our solution: Results Core 1 Core 2 Template before Mix 10 instructions of types: 34%: 33%: 33%: Use entry 1 Signal semaphore 1 Random instructions Poll semaphore 1 Use entry 1 Poll semaphore 2 Use entry 2 Poll semaphore 3 Reconfigure entry 3 Signal semaphore 3 Use entry 2 Random instructions Poll semaphore 1 Reconfigure entry 1 Signal semaphore 1 Reconfigure entry 2 Signal semaphore 2 Use entry 3 Signal semaphore 3 Random instructions Poll semaphore 3 Use entry 3 Random Use entry Reconfigure entry AFTER: Totally random test, now possible BEFORE: Directed test, with synchronization operation

  13. Enabling easy creation of HW reconfiguration scenarios for system level pre-silicon simulation Summary • Existing state-of-the-art constraint random test generator for system-level testing • New hardware requires entry reconfiguration as part of the verification • We implemented automatic barrier insertion that eliminates the need for complex directed tests • The new mechanism allows random generation of tests that use and reconfigure shared entries, with minimal intrusiveness • In the future, the same solution may be applicable for other reconfiguration challenges

  14. Enabling easy creation of HW reconfiguration scenarios for system level pre-silicon simulation For more information, contact:Erez Bilgory (erezbi@il.ibm.com)Alex Goryachev (gory@il.ibm.com)Ronny Morad (morad@il.ibm.com)Tali Rabetti (talis@il.ibm.com)IBM Research – Haifa Thank You!

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