CPSC 668 Distributed Algorithms and Systems

1. CPSC 668Distributed Algorithms and Systems Fall 2009 Prof. Jennifer Welch Set 8: More Mutex with Read/Write Variables

2. Number of R/W Variables • Bakery algorithm used 2n shared read/write variables. • Tournament tree algorithm used 3n shared read/write variables. • Can we do (asymptotically) better, in terms of fewer variables? • No! Set 8: More Mutex with Read/Write Variables

3. Lower Bound on Number of Variables Theorem (4.19): Any no-deadlock mutual exclusion algorithm using read/write variables must use at least n shared variables. Proof Strategy: Show by induction on n there must be at least n variables. For each n, there is a configuration in which n variables are covered: means some processor is about to write to it. Set 8: More Mutex with Read/Write Variables

4. Appearing Quiescent • Two configurations C and D are P-similar if each processor in P has same state in C as in D and each shared variable has same value in C as in D. • A configuration is quiescent if all processors are in remainder section. • To make the induction go through, the configuration whose existence we prove must appear quiescent to a set of processors: • C is P-quiescent if there is a quiescent configuration D such that C and D are P-similar Set 8: More Mutex with Read/Write Variables

5. Warm-Up Lemma Before a processor can enter its CS, it must write to an uncovered variable. Lemma (4.17): If C is pi-quiescent, then there is a pi-only schedule  such that • pi is in CS in (C) and • during exec(C,), pi writes to a variable that is not covered in C. Set 8: More Mutex with Read/Write Variables

6.  D pi in CS by ND quiescent  C pi in CS pi-quiescent Proof of Warm-Up Lemma (a) • Since C is pi-quiescent, it looks the same to pi as some quiescent D. • By ND, some pi-only schedule  exists starting at D in which pi enters CS. • When  starts at C, pi also enters CS. Set 8: More Mutex with Read/Write Variables

7. 1 2  C E Q some pj (not pi) takes steps alone; by ND eventually pjenters CS successively invoke ND to cause all procs to be in remainder; pi takes no step one step by each proc in P; over- writes W Proof of Warm-up Lemma (b) • Suppose in contradiction when  is executed starting at C, pi writes to the set of variables W but all the variables in W are covered in C. • Let P be the set of processors covering the variables in W. Set 8: More Mutex with Read/Write Variables

8.  pi-only, writes to W 1 2  C' E' Q' overwrites W successively invoke ND pj-only pj in CS, pi in CS pi in CS Proof of Warm-up Lemma (b) 1 2  C E Q successively invoke ND pj-only pj in CS overwrites W Contradiction! Only difference between C and C' are the writes by pi, but those values are overwritten in 1so the info is lost. Set 8: More Mutex with Read/Write Variables

9. Main Result For all k between 1 and n, for all quiescent C, there exists D s.t. • D is reachable from C by steps of p0,…,pk-1 only • p0,…,pk-1 cover k distinct variables in D • D is {pk,…,pn-1}-quiescent. implies desired result when k = n Set 8: More Mutex with Read/Write Variables

10. Proof of Main Result - Basis By induction on k. Basis:k = 1. Must show for all quiescent C, there exists D s.t. • D is reachable from C by steps of p0 only • p0 covers a variable in D • D looks quiescent to the other procs. • By warm-up lemma (a), if p0 takes steps alone, it eventually writes to some var. • Desired D is just before p0 's first write. Set 8: More Mutex with Read/Write Variables

11. 0 C C1 only p0 to pk-1 take steps any qui. config. p0 to pk-1 cover W; pk to pn-1qui. pk-only   D1' pk covers x not in W p0 to pk-1 overwrite W, become quiescent pk in entry looks qui. to rest Proof of Main Result - Induction Assume for k, show for k+1. by ind. hyp. by warm-up lemma (b) as in pf. of warm-up lemma Set 8: More Mutex with Read/Write Variables

12.   D1 C2 qui. p0 to pk-1 only p0 to pk-1 cover W; pkto pn-1qui.  C2' p0 to pk cover W and x; pk+1to pn-1 qui. Proof of Main Result - Induction k vars. 0 C C1 only p0 to pk-1 take steps any qui. config. p0 to pk-1 cover W; pkto pn-1qui. by ind. hyp. but why is the same set of k vars covered again? pk-only   D1' pk covers x not in W p0 to pk-1 o'write W, become quiescent pk in entry looks qui. to rest k+1 vars. Set 8: More Mutex with Read/Write Variables

13. Proof of Main Result - Fix • The result of applying  to D1 might result in a different set of k variables, W', being covered instead of W. • If W' includes x, we have not succeeded in covering an additional variable. • To fix this problem, repeatedly apply inductive hypothesis to get C1,D1,C2,D2,C3,D3,… • Since number of variables is finite, there exist i and j such that in Ci and Cjthe same set of k variables is covered. • Then apply same argument as before, replacing C1 and C2 with Ci and Cj. Set 8: More Mutex with Read/Write Variables

14. Fast Mutual Exclusion • The read/write mutex algorithms we've seen so far require a processor to access f(n) variables in the entry section even if no contention. • It would be nice to have a fast algorithm: if no competition, a processor enters CS in O(1) steps. • Even better would be an adaptive algorithm: performance depends on number of currently competing processors, not total number. Set 8: More Mutex with Read/Write Variables

15. Fast Mutual Exclusion • Note that multi-writer shared variables are required to be fast. • Combine two mechanisms: • provide fast entry when no contention • provide no deadlock with there is contention Set 8: More Mutex with Read/Write Variables

16. Contention Detector Overview • A doorway mechanism captures a set of processors that are concurrently accessing the detector • Use a race to choose a unique one of the captured processors to "win" Set 8: More Mutex with Read/Write Variables

17. Contention Detector Uses two shared variables, door and race. Initially door = "open", race = -1. • race := id • if door = "closed" then return "lose" • else • door := "closed" • if race = id then return "win" • else return "lose" Set 8: More Mutex with Read/Write Variables

18. Analysis of Contention Detector Claim: At most one processor wins the contention detector. Why? • Let K be set of procs. that read "open" from door in Line 2. • Let pj be proc. that writes to race most recently before door is first set to "closed". • No node pi other than pj can win: • If pi is not in K, it loses in Line 2. • If pi is in K, it writes race before pj does but checks again (Line 5) after pj 's write and loses. Set 8: More Mutex with Read/Write Variables

19. Analysis of Contention Detector Claim: If pi executes the contention detector alone, then pi wins. Why? • Trace through the code when there is no concurrency. Set 8: More Mutex with Read/Write Variables

20. Ensuring No Deadlock • If there is concurrency, it is possible that no processor wins the contention detector. • To ensure progress: • nodes that lose the contention detector participate in an n-processor ME alg. • The winner of the n-processor alg. competes with the (potential) winner of the contention detector using a 2-processor ME alg. • Winner of 2-processor alg. can enter CS Set 8: More Mutex with Read/Write Variables

21. Ensuring No Deadlock lose contention detector n-proc. mutex win play role of p0 play role of p1 2-proc. mutex critical section Set 8: More Mutex with Read/Write Variables

22. Discussion of Fast Mutex • Be careful about the exit section: contention detector needs to be reset properly • This is a modular presentation: doesn't specify particular n-proc and 2-proc subroutine mutex algorithms • Not adaptive: even if only 2 procs are contending, execute the potentially expensive n-proc algorithm Set 8: More Mutex with Read/Write Variables