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Area Array Research Consortium Lead-Free Soldering Program

Area Array Research Consortium Lead-Free Soldering Program. Anthony Primavera - Program Manager Michael Meilunas - Reliability Mark Dunlap - Assembly Universal Instruments Corporation SMT LABORATORY. Consortium Research Topics. Lead Free Materials Evaluation Wetting of Lead Free Solder

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Area Array Research Consortium Lead-Free Soldering Program

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  1. Area Array Research ConsortiumLead-Free Soldering Program Anthony Primavera - Program Manager Michael Meilunas - Reliability Mark Dunlap - Assembly Universal Instruments Corporation SMT LABORATORY

  2. Consortium Research Topics • Lead Free Materials Evaluation • Wetting of Lead Free Solder • Alternative PCB Pad Finish • Environmental Aging / Process & Storage Conditions • Assembly • Effects of Reflow Profile • Self Centering / Pull back / Solderballing etc. • Mixing of Alloys & Contamination • Reliability Testing • Commercially Available Component • Fabrication of Test Vehicles • Mechanical & Thermal Cycle Tests • Determination of Solder Properties & Crack Growth Rate • FEM Modeling

  3. Reliability Testing Timeline • Year 2000 Consortium • Few Commercial Components Available • Lead Free CSP/BGAs In Development • Designed & Fabricated Generic Test Vehicles (Early 2000) • Initial Testing Program I Begins (Mid 2000) • Accelerated Thermal Cycle Testing of Lead Free BGAs • Presentation of Initial Test Results for ATC (Late 2000) • Year 2001 Consortium • Follow on ATC Program II for Generic Lead Free BGAs • Testing of Several Commercial Lead Free CSP/BGAs • Development & Test of Generic Lead Free CSPs • Year 2002 Consortium • Wrap up of ATC Program II • Follow on ATC Program III - Commercial & Generic BGAs

  4. Early Results (Year 2000) • Accelerated Thermal Cycle • 0-100oC • 20 min (5 min ramp & dwell) • Continuous event detection • Identification of electrical events • Events not consistent with Sn/Pb solder fatigue ATC event detection • Identification of failed joint difficult • Events sporadic throughout testing • Crack / Fatigue • Sn/Pb baseline components failed by typical fatigue cracking • lead-free solder joints have “unique shattered appearance” • Lead-free cracks are multidirectional and are often very fine

  5. Glitch or Electrical Event • A glitch or event is defined as a false or spurious electronic signal. • BGA devices that were continuously monitored while in thermal cycle displayed resistance “spikes” that sporadically occurred over several hundred cycles. These “spikes” were observed in Sn/Ag and Sn/Ag/Cu solder joints with nickel layers on both the component and printed circuit board pads. Cu Ni Ni Cu

  6. Test Vehicle: FCPBGA • 256 I/O Daisy Chain • Utilizes Electroless Ni/ Immersion • Au Pad Finish • 0.030” Diameter Spheres • 0.003” Encapsulant • 0.016” Laminate Substrate • 0.030” Glass Die • CTE of 11.1ppm/°C • (Moiré Interferometry) • Assembled to 0.062” FR-4 Based PCBs Glass Die Solder Bumps Encapsulant Layer

  7. Generic Flip Chip PBGA (FCPBGA) Test Package BUMPED SUBSTRATE ( 30 mil Dia Solder Sphere, 1.1”Square Substrate with 256 BGA pattern) COPPER PAD ATTACHMENT (Copper Pads - 3 mils thick; used to obtain an uniform standoff) ENCAPSULANT DISPENSE ON SUBSTRATE (Encapsulant used : Namics 8437-2)

  8. Generic Flip Chip PBGA (FCPBGA) Test Package GLASS PLACEMENT : Use of Glass Placement Fixture to center the die on the Substrate

  9. Generic Flip Chip PBGA (FCPBGA) Test Package Unbalanced Component Component utilized in ATC Testing Both In-plane and out-of-plane deformation Balanced Component Component utilized in Crack Growth Rate Study. Predominately in-plane deformation Samples tested every N cycles in ATC, then subject to dye penetration testing Goal: correlation of crack area with number of thermal cycles

  10. Assembly of Test Vehicles • Consortium CSPTB2 • 4 Layer Construction: 2 Signal, 2 gnd • Tetrafunctional FR4 170oC Tg • Taiyo Prs4000 Mask • 0.062” Nominal Thickness • 2 Assembly Sites • 21 Mil Circular Pads • 26 Mil Mask Opening • 23 Mil Circular Pads • 28 Mil Mask Opening

  11. Assembly of Test Vehicles CSPTB2 • Solder paste stencil • 5 mil thick stainless steel • Laser cut apertures, approximately 0.5 mil taper • Circular apertures • 21 mil circular pads • 22.2 mil mean, 0.2 mil std dev. (top side) • 22.8 mil mean, 0.2 mil std dev. (bottom side) • Aperture Volume = 2005 cubic mils • Solder Volume = 14,932 cubic mils • 23 mil circular pads • 24.2 mil mean, 0.2 mil std dev. (top side) • 24.6 mil mean, 0.3 mil std dev. (bottom side) • Aperture Volume = 2337 cubic mils • Solder Volume = 15,065 cubic mils 0.03” Sphere 14,130 cubic mils Approximately 80% transfer &50% solidified paste volume Vcone = 1/3h(r12 +r22 + r1r2)

  12. Experimental Test Matrix 1

  13. Test Equipment • Thermotron ATS 150 • Two Zone Thermal Shock Chamber • Thermal Cycle: 0 to 100°C • 5 Minute Ramps • 5 Minute Dwells • Anatech 256 Event Detector • Resistance Monitor • 1.2mA Current (Fixed) • 300 Threshold (UIC Setting) • 200nS Sample Frequency (Fixed) • PC • Data Logging

  14. Failure Criteria • IPC-SM-785 Section 7.8: • “Failure is defined as the first interruption of electrical continuity that is • confirmed by 9 additional interruptions within an additional 10% of the cyclic life.” • Event: • Electrical continuity interruption. Daisy chain loop resistance exceeds: • 300 , for >200nanoseconds UIC Criteria • 1000  for >1microsecond - IPC Criteria • Maximum 15 events per cycle. The frequency of the events per cycle • increases as solder fracture increases.

  15. Test Results (Matrix 1) • Thermal cycling with no events until ~2700 cycles. • Lead free FCPBGA packages began to demonstrate “Failure” characteristics. • The samples were electrically continuous when tested with multimeter probe. • Samples were cross sectioned or subject to a dye penetration test. • Fracture surfaces were minimal. • The remaining samples were returned to thermal cycling. • The electrical events were continued sporadically. • Sn/Pb packages exhibited no failures.

  16. Onset of Glitch vs. Confirmed Open

  17. Failure Analysis • Cross Sections of Glitch Failures • Extremely fine cracks • Incomplete Cracking Sn/Ag/Cu on Ni/Pd 3500 Cycles Sn/Ag Alloy on Ni/Pd PCB 3500 Thermal Cycles

  18. Test Result Verification • Noise Control: • New ground wires to the chamber, Anatech and PC were installed. • Anatech and PC wire shielding was replaced. • Placement within the chamber was rearranged. • Packages were firmly taped in place to minimize vibration. • Problem persisted. • Manual Monitoring: • Visually (continuously) monitored Anatech output. • Noted that events occurred after basket transitions during the ramp up phase.

  19. Test Result Verification • Glitches Identified in 4 Groups: • Sn/Ag/Cu on Ni/Au PCB • Sn/Ag on Ni/Au PCB • Sn/Ag on Ni/Pd PCB • Sn/Ag/Cu on Ni/Pd PCB • Apparent Trends: • All packages were bumped with Ag bearing alloys • Both PCB finishes contained Electroless Nickel • Events occurred in the ramp up phase • Sn/Pb samples showed no glitch / events • Sample assembled on Cu OSP pads showed no glitches • Samples Pulled from Test: • Sn/Ag on Ni/Pd (4) • Sn/Ag/Cu on Ni/Au (4) • Sn/Ag on Ni/Au (3) • Sn/Ag/Cu on Ni/Pd (1)

  20. Confirmation Experiments • Reworked Samples • 29 reworked samples submitted for reliability testing • 26 packages utilized a Cu OSP pad finish • 3 utilized Sn/Ag Alloy on Ni/Pd pad finish • Glitch detected in 2 of the Sn/Ag on Ni/Pd samples • Occurred between 2000 and 2250 cycles • Tests were Conducted on Existing Samples: • High temperature Probe • Oscilloscope monitoring • Resistance recording • Circuit reliability test • Elemental analysis

  21. Characterization Experiments • High Temperature Probe • Sample set on a hotplate (115°C) • Standard multimeter used • No opens located • Resistance changes noted

  22. Characterization Experiments • Oscilloscope • Sample set on a hotplate (115°C) • Constant 10mA current applied • Continuous data of Voltage vs. Time • Glitch detected Sn/Ag on Ni/Pd (3500 Cycles)

  23. Characterization Experiments • Resistance Recording • Sample set on a hotplate (115°C) • Source Meter (10mA, 40mS Freq.) • Resistance spikes noted • Measured Events • Resistance spikes as small as 5-10  • Duration on order of nanoseconds. 25 Resistance vs. Time Sn/Ag on Ni/Pd 20 15 Ohms 10 5 0 50 100 150 200 250 Time (sec)

  24. Characterization Experiments • Circuit Reliability Tester • Detects line reduction (Cracks) • Hotplate used to heat packages • Failures located • Corner solder joints • SEM Analysis • Cross sectioned to failure locations • Performed elemental analysis Glitch Sample : Sn/Ag on Ni/Pd - 3500 Cycles Full Open Sn/Ag on Ni/Pd 8000 Cycles

  25. Lead Free Crack Propagation Test • Balanced Construction • Samples Subjected to 0-100C ATC • 20 min test 5 min ramp and dwell • Samples pulled from test at fixed times • Samples subjected to dye penetration test • Goal: • Measure crack growth rate for lead free alloys

  26. Failure Analysis: Dye Penetration Testing Place in vacuum (>/= 9 in Hg) for 1 minute then allow to soak for 1 hour Immerse in dye Dry dye at 100 C for 30 minutes Separate component by twisting of PWB Typical Sn/Pb Failure

  27. Lead Free Crack Growth Sn/Ag • Results: • No clear growth rate measured • Dye failed to fully penetrate cracks • Cracking fundamentally “different” • than Sn/Pb fatigue cracks Sn/Ag/Cu Sn/Ag/Cu/Sb

  28. Test Matrix 2 - Year 2001 follow on A focus group was initiated to continue evaluation of lead free BGAs in a “round robin” set of tests UIC, IBM, Nokia, Motorola, Rockwell-Collins

  29. Test Goals • Confirmation of Test 1 results • Evaluation of Lead-free BGAs under different ATC conditions • Evaluation of Alternative PCB finishes • Test Differences • Round 1 • NSMD Component Pads • 1 ATC cycle (0-100C 20 min) • 30 mil thick glass die (more warpage?) • PCB pad finish - OSP, Ni/Au, Ni/Pd • Round 2 • SMD Component Pads • Different Thermal Cycles • 40 mil thick glass die • PCB pad finish - OSP, Ni/Au, Imm Ag

  30. Round 2 • ACT Test Conditions: • Continuous Event Detection • 300 Resistance Threshold, 200 nanoseconds • Universal 0-100C, 20 min : 5 min ramp and dwell • IBM 0-100C,  32 minute: 7.5 min ramp, 8 min dwell • Motorola 0-100C, 30 minute: 10 min ramp , 5 min dwell • Nokia -40-125C, 60 minute: 15 min ramp and dwell • Rockwell Collins -55-125C, 71 minute: approximately 15 min dwell* • Assembly: • UIC fabricated all test components & provided solder ball bumping • UIC supplied PCBs, components and solder paste to each participant • Each participant assembled the component to PCB (UIC TB6)

  31. Assembly of Test Vehicles • Consortium CSPTB6 • 4 Layer construction: 2 Signal, 2 gnd • Tetrafunctional FR4 175oC Tg • Taiyo Prs4000 mask • 0.062” nominal thickness • Assembly locations • 20 mil circular pads • 2 sites 25 mil mask opening • 22 mil circular pads • 4 sites 26 mil mask opening • 24 mil circular pads • 2 sites 28 mil mask opening

  32. Assembly of Test Vehicle CSPTB6 • Solder paste stencil - Square apertures • Laser cut 5 mil thick stainless steel • 20 mil circular pads • 19.1 mil mean, 0.1 mil std dev. (top side) • 20.1 mil mean, 0.1 mil std dev. (bottom side) • Aperture Volume = 1922 cubic mils • Solder Volume = 14,995 cubic mils • 22 mil circular pads • 21.2 mil mean, 0.1 mil std dev. (top side) • 22.2 mil mean, 0.1 mil std dev. (bottom side) • Aperture Volume = 2356 cubic mils • Solder Volume = 15,190 cubic mils • 24 mil circular pads • 23.2 mil mean, 0.2 mil std dev. (top side) • 24.1 mil mean, 0.2 mil std dev. (bottom side) • Aperture Volume = 2798 • Solder Volume = 15,389 0.03” Sphere 14,130 cubic mils Approximately 90% transfer & 50% solidified paste volume Vtrap = h(l1w1 + l2w2)/2

  33. Assembly of Test Vehicle CSPTB6 Assembly Results • UIC • Several components showed underfill to die • delamination, due to insufficient pre-bake. • Several “Ni/Au” component early failures • Nokia • Voids observed in Sn/Ag/Cu/Sb samples • Several “Ni/Au” component pad early failures • Rockwell-Collins • Sn/Ag/Cu paste utilized in all combinations. • IBM • Several “Ni/Au” component pad early failures • Motorola • Several “Ni/Au” component pad early failures

  34. General Round 2 Information SAC on ImmAg • Testing completed “substantial” • number of cycles at each location • UIC > 16,700 cycles • Nokia > 7,000 • Motorola > 13,700 • Rockwell > 2,000 • IBM > 13,500 • Cracking - Fine in appearance, • multiple crack fronts and paths • Failure time - earlier on Ni/Au • than OSP for some test cells. • “Glitch behavior” noted in • several lead free BGAs with Ni/Au pads SA on ImmAg

  35. Failure on ImmAg - Rockwell Collins • -55 to 125C ATC • Failure near Cu-Sn intermetallic layer • High amounts of Sn-Ag near cracks • Cracks “go around” Sn-Ag plates • Micro-voiding observed near crack SnAgCu on ImmAg 1544 cycles Sn-Ag Micro Voids Cu-Sn SnAg on ImmAg 1528 cycles

  36. Confirmation of Glitch Behavior? • “Glitch behavior” - Sporadic events for >100’s of cycles • Motorola • 2 samples Sn/Ag/Cu on Ni/Au pads • UIC (note most samples pulled from test after first events) • 2 samples Sn/Ag/Cu on Ni/Au pads • 1 sample Sn/Ag/Cu/Sb on Ni/Au • Nokia • 1 sample Sn/Ag/Cu on Ni/Au pads • 1 sample Sn/Ag on Ni/Au pads • 1 sample Sn/Ag on OSP pads • 2 samples Sn/Ag/Cu/Sb on Ni/Au pads • 1 sample Sn/Ag/Cu/Sb on OSP

  37. Other Lead Free Testing - Generic FCCSP • Generic CSP size package • 0.8 mm pitch 64 I/O • Similar construction to generic BGA • 0.02” lead free & Sn/Pb solder bumps • Assembled on OSP, Ni/Au and ImmAg PCBs • 0-100C ATC testing • Mixed assembly (ie. SAC bump & Sn/Pb paste) • Samples through 8,000 cycles

  38. FCCSP Test Results Sn/Ag/Cu/Sb on ImmAg • Lead-free solder samples show • similar crack behavior to BGA testing • Mixed samples showed some failures • at Ni layer Ag-Sn intermetallic Cu-Sn intermetallic Early Fail (<2000 cycles) Near Ni layer Sn/Ag/Cu/Sb/Pb mixed on Ni/Au

  39. Generic FCCSP Test Results Ag-Sn Early Failure on ImmAg In general ATC - OSP> NiAu Similar to BGA data on ImmAg FCCSP Data - 7,000 cycles Failure near and around intermetallic layers Presence of micro voids Cu-Sn Micro Voids Sn/Ag/Cu on ImmAg Good joint approximately 2500 cycles

  40. FCCSP ACT Results 0-100C Predicted OSP failure with B=5 OSP Data Set not enough fails for accurate plot

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