Bosch Process Characterization for Donut TSV’s

1. Bosch Process Characterization for Donut TSV’s John Slabbekoorn, Bart Schepers, Khashayar Babaei Gavan, Stefano Sardo, Stefaan Van Huylenbroeck, Tom Vandeweyer,Kenneth June Rebibis, Andy MillerIMEC Warren W. Flack, Robert Hsieh, Manish RanjanUltratech, Inc.

2. Outline • Introduction • Donut Via Last Process • Characterization of Lithography • Characterization of Deep Silicon Etch • Etch depth determination • Conclusions

3. 3D IC with TSV Adoption Timeline Highlights • Image sensors have been one of the early device adopters for via last technology • There is continued interest from end products for future adoption of TSV technology Key Demand Drivers Source: TechSearch International, Inc.

4. Introduction • Traditional TSV Last effectively requires 2 etching steps –Si etch followed by dielectric etch. Charging effect causes notching when landing with main Si etch on di-electric Si Si STI/PMD oxide etch to M1 Si TSV etch Scalloping Residue Notching Si Si carrier Si carrier oxide

5. Use of Donut TSV • No liner opening at the bottom of the TSV required after Si etch • No impact of lateral etching of Si • Thick polymer liner reduces TSV capacitance and stress • Three litho steps required • Scalability Si 50µm 3 µm 5-10µm Si carrier

6. Outline • Introduction • Donut Via Last Process • Characterization of Lithography • Characterization of Deep Silicon Etch • Etch depth determination • Conclusions

7. Donut Via Last Process Si Thinned wafer on carrier Si carrier

8. Donut Via Last Process Si Si Si “Donut” etch (Bosch) Definition of this trench is the topic of this presentation Si carrier Si carrier

9. Donut Via Last Process Si Si Si Polymer trench Fill Si carrier Si carrier Si carrier

10. Donut Via Last Process Si Si Si Si Polymer & Pass dry etch Si carrier Si carrier Si carrier Si carrier

11. Donut Via Last Process Si Si Si Si Si Core Si TSV etch + oxide opening Si carrier Si carrier Si carrier Si carrier Si carrier Core of the Donut is removed

12. Donut Via Last Process Si Si Si Si Si Regular PVD Barrier/Seed & bottom-up ECD Cu fill + CMP Si carrier Si carrier Si carrier Si carrier Si carrier Si Si carrier

13. Donut Via Last Process Challenges in etching Ideal Trench Definition Notching when landing on Pre-Metal-Dielectric Aspect Ratio Dependent Etch rate (ARDE) Influence of variation in lithography? profile with main etch & soft landing etch

14. Outline • Introduction • Donut Via Last Process • Characterization of Lithography • Characterization of Deep Silicon Etch • Etch depth determination • Conclusions

15. Characterization of Lithography • Wafer & Stack • 300mm • thin passivation layer • Photoresist process • AZ10XT coated to a thickness of 7.5µm • Development with diluted AZ400k 1:4 • Reticle • Litho Test Reticle with varying dimensions • Exposure • AP300 stepper • using GH-line illumination • Metrology • Top down CD SEM • Cross sectional SEM

16. Characterization of Lithography • Cross-section of circular trench is never perfectly vertical. • For evaluation long linear trenches are used

17. Characterization of Lithography X-SEM example of a 2.4µm resist trench. Complete analysis is performed by CD-SEM measuring top CD and bottom CD Focus Exposure Matrix

18. Characterization of Lithography Top-CD • Data for 2.4µm trenches in resist. • Print Bottom CD 5% larger than design for stability • Top & bottom behave different with top overexposed and a small focus shift • Process window for 2.4µm trenches is very large Bottom-CD

19. Characterization of Lithography • X-SEM and simulation of a 2.4µm resist trench. • Prolith™ simulation of resist trench matches well to experimental results • Modeling can be used to investigate enhancements to the process and minimize experimental work

20. Outline • Introduction • Donut Via Last Process • Characterization of Lithography • Characterization of Deep Silicon Etch • Etch depth determination • Conclusions

21. Characterization of Deep Silicon Etch Samples Cross-sections of main etch profiles Sample Cross-section of main and soft landing etch profile • ARDE effect visible • Soft landing etch has sloped profile

22. Characterization of Deep Silicon Etch • At 3µm CD the ARDE effect is minimal for the main etch. • The “soft landing etch” has a Resist slope has small effect on etch rate • Larger features are more sensitive and would require a lower limit on slope • larger ARDE effect

23. Outline • Introduction • Donut Via Last Process • Characterization of Lithography • Characterization of Deep Silicon Etch • Etch depth determination • Conclusions

24. Impact of Si thickness Si Landing etch is less well defined and etch time needs to be minimized. Si Allow safety margin for thickness and etch variation Si carrier Soft landing etch requires ~ 100% over etch time to ensure all remaining Si removed above PMD. Si carrier

25. Etch depth determination

26. Outline • Introduction • Donut Via Last Process • Characterization of Lithography • Characterization of Deep Silicon Etch • Etch depth determination • Conclusions

27. Conclusions • The lithographic process window is suitably large to enable a well controlled Donut style TSV last approach • Nominal 2.4 µm trenches translate well to annular rings • Typical resist sidewall angles have a small effect on trench depth and profile after etch. • Impact of Aspect Ratio Dependency at nominal 2.4µm feature size is twice that at nominal 3.0µm. • Process window requirements at etch are dominated by wafer grinding effects • Post grinding mean thickness plus TTV • Wafer to wafer and batch to batch variation • Trench definition is feasible with good process control ACKNOWLEGEMENTS: Patrick Jaenen, Inge de Preter and Filip Beirnaert For advice and X-SEM