Microprocessors

1. Microprocessors The MIPS Architecture (User Level Instruction Set) Mar 21st, 2002

2. Generations of MIPS • Original architecture R2000 • Later version R3000-R10000 • Added instructions • Moved from 32-bit to 64-bit • Doubled number of fpt registers • Removed some restrictions • Removed features inhibiting high performance • We will look at the R2000 here

3. Overall Characteristics • Byte Addressed Memory • 32-bits = 4 gigabytes max memory • Configurable on reset to big/little-endian • Normally run in big-endian mode • Registers • 32 x 32 integer registers • Multiply/divide registers HI/LO (32 bits) • Program Counter 32 bits

4. More on Registers • Register 0 is special • Reads as zero bits • Discards any write attempts • Registers 31 is special • It is the link register for CALL instruction

5. More on Memory • In user mode, 2 gigs addressable • Positive addresses from 0 to 7FFF_FFFF • Memory is mapped and cached • In system mode • User memory mapped and cached as above • 8000_0000 – 9FFF_FFFF (cached only, maps to first 0.5 gig of physical memory) • A000_0000 – BFFF_FFFF (not cached, maps to first 0.5 gig of physical memory) • C000_0000 – FFFF_FFFF (mapped and cached)

6. Instruction Execution • Uses 5-stage pipeline • IF instruction fetch • RD decode and read register values • ALU perform required operation • MEM access memory • WB write back results to registers • One clock per pipe line stage

7. Pipeline Configuration • R2000 Instruction Pipeline • IF RD ALU MEM WB IF RD ALU MEM WB IF RD ALU MEM WB • One instruction enters pipeline on each clock

8. Interface to Memory • External Cache memory • First chip with large cache memory • Separate cache for memory and instructions • Allows fetching instruction and data in same clock • Write Buffer • All data is written to write buffer • Reads go through write buffer • To ensure serial consistency

9. Instruction Formats (One Slide!) • All instructions are 32 bits • I-type (Immediate) • op rs rt immediate 6 5 5 16 • J-type (Jump) • op target 6 26 • R-type (Register) • op rs rt rd shamt funct 6 5 5 5 5 6

10. I-Type Instruction • I-type (Immediate) • op rs rt immediate 6 5 5 16 • The opcode is always first 6 bits • The rs field is source register • The rt field is target register • The immediate field is a 16-bit signed val • Used for reg instructs: rt := rs op immed • Used for load/stores: rt is register loaded/storedAddress for load store is rs (base) + offset • Used for conditional jump instructions: rs, rt areregisters tested, immediate is a 16-bit signed offset

11. More on Load/Stores • Addressing modes are • Immediate (first 32K of memory, really useful only for operating system), base = 0 • Register indirect. Base is the register, offset is set to zero. • Register+offset. Base is the register, offset gives a +/- 32K offset from this register

12. J-Type Instruction • J-type (Jump) • op target 6 26 • The opcode is always first 6 bits • Target is 28 bit address (last 2 bits zero) • Used for unconditional jumps/calls • Can only address 256 megabytes • Upper 4 bits of PC is unchanged

13. R-Type Instruction • R-type (Register) • op rs rt rd shamt funct 6 5 5 5 5 6 • Opcode is always first 6 bits • Typical use is rd  rs (op) rt • (op) is determined by op+funct fields • shamt is shift amount for shift instructions

14. The Instruction Set • The following slides cover the entire user level instruction set of the MIPS R2000 • Contrast this with the extensive instruction set of CISC chips (or modern RISC chips!)

15. Load Instructions • LB - Load byte, sign extended • LBU – Load byte, zero extended • LH – Load halfword, sign extended • LHU – Load halfword, zero extended • LW – Load word • LWL – Load word left • LWR – Load word right

16. Notes on Sign/Zero Extension • Sign extend means copy sign bits • For example, for LB, if memory has FE (-2) then 32-bit register will have FFFF_FFFE (which is also -2) • Zero extend means supply zero bits • For example, for LB, if memory has FE (-2 or 254 depending on how you look at it), register wil have 0000_00FE (254)

17. Notes on Load Left/Right • Memory references must be aligned • Load Left/Load Right allow a non-aligned word to be loaded in two separate instructions • Load left loads left bytes of register • Load right loads right bytes of register

18. Load Delay Slot • Instruction immediately after a load cannot reference the loaded register • If it does reference it, then result is undefined. • Idea is that if data is in cache, then no need to delay or interlock (1 clock is enough time to get the data) • If data is not in cache, pipeline will stall

19. Store Instructions • SB – Store byte • SH – Store halfword • SW – Store word • SWL – Store word left • SWR – Store word right • SWL/SWR allow storing of non-aligned word in two instructions

20. Computational Immediate • ADDI – Add immediate • ADDIU – Add immediate unsigned • SLTI – Set on less than immediate • SLTIU – Set on less than immediate (uns) • ANDI – And immediate • ORI – Or immediate • XORI – Exclusive or immediate • LUI – Load upper immediate

21. Note on Set Instructions • For the set instructions • A comparison is done (signed or unsigned) on the two source values (register and immediate, or register/register) • The result register has 0 or 1 depending on whether the less than condition is false or true (same values as used by C language)

22. Note on Load Upper Immediate • LUI – Load Upper Immediate • The immediate value is loaded into the upper 16 bits of the target register, lower 16 bits are set to zero. • Use with following ORI to set full 32-bit immediate value (e.g. an address).

23. Note on signed/unsigned add • For add/subtract instructions • Signed instructions trap on signed overflow • Unsigned instructions do not trap • Result is same (in the absence of trap) • 2’s complement used for signed values

24. Computational Reg/Reg • ADD – Add registers • ADDU – Add registers unsigned • SUB – Subtract registers • SUBU – Subtract registers unsigned • SLT – Set on registers less than • SLTU – Set on registers less than unsigned • AND – Logical and registers • OR – Logical or registers • XOR – Logical exclusive or registers • NOR – Logical nor registers

25. Shift Instructions (fixed count) • Here rt is input, rd is output, shamt is shift count in bits • SLL – Shift left logical (zero fill) • SRL – Shift right logical (zero fill) • SRA – Shift right arithmetic (sign bit fill) • Note this not quite an ordinary divide, since -5 shifted right one bit gives -3, not -2

26. Shift Instructions (variable count) • For these instructions, rt is input register, rd is output register, low 5 bits of rs is shift amount • SLLV – Shift left logical variable • SRLV – Shift right logical variable • SRAV – Shift right arithmetic variable

27. Multiply/Divide Instructions • For these, input is in rs,rt, result in HI/LO • MULT – Signed multiply • MULTU – Unsigned multiply • For these, rs is dividend, rs is divisorLO gets quotient, HI gets remainder • DIV – Signed divide • DIVU – unsigned divide

28. Accessing HI/LO registers • MFHI – Move from HI to rd • MFLO – Move from LO to rd • MTHI – Move from rd to HI • MTLO – Move from rd to LO • Note: for the move from instructions, there is an interlock to wait for completion of the (relatively long) divide/multiply

29. Jump Instructions • J – Unconditional jump (26 bit target) • JAL – Jump and link (26 bit target, R31 set to instruction address + 8) • JR – Jump Register (target is in rs) • JALR – Jump and link register (target in rs, rd set to instruction address + 8)

30. Branch Instructions • All these instructions use rs/rt as input instructions and the target is in offset • BEQ – Branch on Equal, branch if rs = rt • BNE – Branch on Not Equal, branch if rs /= rt • BLEZ – Branch on LE zero, branch if rs <= 0 • BGTZ – Branch on GT zero, branch if rs > 0 • BLTZ – Branch on LT zero, branch if rs < 0 • BGEZ – Branch on GE zero, branch if rs >= 0 • BLTZAL – Branch and link on LT zero • BGEZAL – Branch and link on GE zero • Note: last two instructions set 31 to instruc + 8

31. Jump/Branch Delay Slots • All jumps and branches have a delay slot • This slot is unconditional • The instruction in the delay slot is executed logically before the jump • Jump cannot depend on value from instruction in delay slot • This is why link register set to instruction + 8, since that is the return point

32. Special Instructions • SYSCALL • Initiates system call trap • Parameters passed in registers (like Int 21 in DOS on the ia32) • Transfers control to system exception handler • BREAK • Initiates breakpoint trap • Transfers control to system exception handler

33. That’s All Folks! • This is slide 33 • And we have done the ENTIRE MIPS user level instruction set without any omissions • Well we left out floating-point, but technically that is the coprocessor, not the MIPS processor itself.