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Multi-core processors

Multi-core processors. 12/1/09. Multiprocessors inside a single chip. It is now possible to implement multiple processors (cores) inside a single chip. The number of cores in multicore processors is expected to double every two years. Manycore processors will become the norm.

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Multi-core processors

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  1. Multi-core processors 12/1/09

  2. Multiprocessors inside a single chip • It is now possible to implement multiple processors (cores) inside a single chip. • The number of cores in multicore processors is expected to double every two years. • Manycore processors will become the norm. • Such processors typically share some of the caches and external memory interfaces. • Eliminates latencies associated with chip-to-chip communications.

  3. Applications • In some multi-core applications processors are running the same code. • SIMD • Multithreading • State of tread must be saved when a processor switches to a new thread. • Requires separate copies of registers.

  4. Multithreading • Fine-grained multithreading • Course-grained multithreading • Simultaneous multithreading (SMT)

  5. Fine-grained multithreading • Switches between threads on each clock. • Interleaved execution of threads. • Must be able to switch threads very quickly. • On each clock • Stalled threads are skipped • Primary disadvantage is that execution of any particular thread is slowed since it is interleaved with other threads.

  6. Course-grained multithreading • Invented as an alternative to fine-grain multithreading • Switches threads only on costly stall. • Such as level 2 cache miss • Relieves need to switch threads on each clock. • Less likely to slow execution of an individual thread. • Disadvantage • Throughput suffers because of inability to switch threads on shorter stalls. • Pipeline must be empted (or frozen) and started up when a thread is switched.

  7. Simultaneous multithreading • A variation of multithreading • Uses a multiple-issue, dynamically scheduled processor to exploit thread-level parallelism at the same time exploiting instruction-level parallelism. • Motivated by the fact that modern multiple-issue processors often have more functional unit parallelism than can be used by a single thread. • Register renaming and dynamic scheduling enable multiple instructions from independent treads without regard to the dependencies among them. • Dependencies are resolved by the dynamic scheduling capability.

  8. Example: Four threads executing independently on a superscalar processor with no multithreading support.

  9. Example: The same four threads executing together on the a processor for the three types of multithreading. Thread A Thread A Thread B Thread A Thread B Thread B

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