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CMPE 3 2 5 Computer Architecture II

CMPE 3 2 5 Computer Architecture II. Cem Erg ün Eastern Med iterranean University. Multiplication & Division Algorithms. Binary Multiplication. At each step we multiply the multiplicand by a single digit from the multiplier.

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CMPE 3 2 5 Computer Architecture II

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  1. CMPE 325 Computer Architecture II Cem Ergün Eastern Mediterranean University Multiplication & Division Algorithms

  2. Binary Multiplication • At each step we multiply the multiplicand by a single digit from the multiplier. • In binary, we multiply by either 1 or 0 (much simpler than decimal). • Keep a running sum instead of storing and adding all the partial products at the end. Multiplication & Division Algorithms

  3. Multiplication • Long-hand multiplication (12 × 9 = 108) 1 1 0 0 = 12ten (n bit Multiplicand) × 1 0 0 1 = 9ten (m bit Multiplier) ----------------------- 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 + 1 1 0 0 0 0 0 ----------------------- 1 1 0 1 1 0 0 = 108ten (n + m bit Product) • The result is a number that is n + m - 1 bits long Multiplication & Division Algorithms

  4. Implementing Multiplication • Several different ways to implement • Things to note about previous method • At each step we either copied or set the value to 0 • LSBs of the product don’t change once computed Can form product by shifting and adding • Solution #1 • Shift multiplicand left at each step (same as adding 0’s) • Shift multiplier right so we can always consider the 0’th bit Multiplication & Division Algorithms

  5. Solution #1 • Multiplication without sign (12 × 9 = 108) 1 1 0 0 = 12ten (n bit Multiplicand) × 1 0 0 1 = 9ten (m bit Multiplier) ----------------------- 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 + 1 1 0 0 0 0 0 ----------------------- 1 1 0 1 1 0 0 = 108ten Multiplicand 0 0 0 0 1 1 0 0 Multiplier 1 0 0 1 Product 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 0 0 1 0 0 0 0 1 1 0 0 0 0 0 1 1 0 0 0 1 0 0 1 0 0 0 0 1 1 0 0 0 0 1 1 0 0 0 0 1 0 0 1 0 0 0 0 1 1 0 0 0 1 1 0 0 0 0 0 1 0 0 1 0 1 1 0 1 1 0 0 Multiplication & Division Algorithms

  6. 1 . T e s t M u l t i p l i e r 0 1 a . A d d m u l t i p l i c a n d t o p r o d u c t a n d p l a c e t h e r e s u l t i n P r o d u c t r e g i s t e r 2 . S h i f t t h e M u l t i p l i c a n d r e g i s t e r l e f t 1 b i t 3 . S h i f t t h e M u l t i p l i e r r e g i s t e r r i g h t 1 b i D o n e Solution #1: Operations S t a r t M u l t i p l i e r 0 = 1 M u l t i p l i e r 0 = 0 t N o : < 3 2 r e p e t i t i o n s 3 2 n d r e p e t i t i o n ? Y e s : 3 2 r e p e t i t i o n s Multiplication & Division Algorithms

  7. Iter Step Multiplier Multiplicand Product 0 Initial Values 1001 0000 1100 0000 0000 1 Multiplier[0]=1  Prod+Mcand 1001 0000 1100 0000 1100 Shift multiplicand left 1001 0001 1000 0000 1100 Shift multiplier right 0100 0001 1000 0000 1100 2 Multiplier[0]=0  Do nothing 0100 0001 1000 0000 1100 Shift multiplicand left 0100 0011 0000 0000 1100 Shift multiplier right 0010 0011 0000 0000 1100 3 Multiplier[0]=0  Do nothing 0010 0011 0000 0000 1100 Shift multiplicand left 0010 0110 0000 0000 1100 Shift multiplier right 0001 0110 0000 0000 1100 4 Multiplier[0]=1  Prod+Mcand 0001 0110 0000 0110 1100 Shift multiplicand left 0001 1100 0000 0110 1100 Shift multiplier right 0000 1100 0000 0110 1100 Solution #1: Example Multiplication & Division Algorithms

  8. Solution #1: Hardware Shift Left Multiplicand 64 bits Shift Right Add Multiplier 64-bit ALU 32 bits Write Product Control 64 bits Multiplication & Division Algorithms

  9. Adjustments to Algorithm 1 • One big problem with the algorithm/implementation shown: • need a 64 bit ALU (adder). • Half of the multiplicand bits are always 0 • Either high or low bits are 0, even as shifted • LSB of product never changes once set • Half of the 64 bit adder is therefore wasted • We can fix this by: • Leaving the multiplicand alone (don’t shift). • Instead of shifting multiplicand left, shift the product right • Add multiplicand to left half of running sum. • Adder only needs to be 32 bits wide Multiplication & Division Algorithms

  10. S t a r t M u l t i p l i e r 0 = 1 M u l t i p l i e r 0 = 0 1 . T e s t M u l t i p l i e r 0 1 a . A d d m u l t i p l i c a n d t o t h e l e f t h a l f o f t h e p r o d u c t a n d p l a c e t h e r e s u l t i n t h e l e f t h a l f o f t h e P r o d u c t r e g i s t e r 2 . S h i f t t h e P r o d u c t r e g i s t e r r i g h t 1 b i t 3 . S h i f t t h e M u l t i p l i e r r e g i s t e r r i g h t 1 b i t N o : < 3 2 r e p e t i t i o n s 3 2 n d r e p e t i t i o n ? Y e s : 3 2 r e p e t i t i o n s D o n e Solution #2: Adjusted Algorithm Revised Addition Shift partial sum instead of multiplicand Multiplication & Division Algorithms

  11. Iter Step Multiplier Multiplicand Product 0 Initial Values 1001 1100 0000 0000 1 Multiplier[0]=1  Prod+Mcand 1001 1100 1100 0000 Shift product right 1001 1100 0110 0000 Shift multiplier right 0100 1100 0110 0000 2 Multiplier[0]=0  Do nothing 0100 1100 0110 0000 Shift product right 0100 1100 0011 0000 Shift multiplier right 0010 1100 0011 0000 3 Multiplier[0]=0  Do nothing 0010 1100 0011 0000 Shift product right 0010 1100 0001 1000 Shift multiplier right 0001 1100 0001 1000 4 Multiplier[0]=1  Prod+Mcand 0001 1100 1101 1000 Shift product right 0001 1100 0110 1100 Shift multiplier right 0000 1100 0110 1100 Solution #2: Example Multiplication & Division Algorithms

  12. Solution #2: Hardware Multiplicand 32 bits Shift Right Add Multiplier 32-bit ALU 32 bits Shift Right Product Control Write 64 bits Upper 32 bits Multiplication & Division Algorithms

  13. Issues and Alternative • In the implementation of the adjusted algorithm it is possible to save space by putting the multiplier in the rightmost 32 bits of the product register. • If you notice, half of the product register is useless at the beginning • At the end, the multiplier register becomes useless • Solution #3 The algorithm is the same, but steps 2 and 3 are done at the same time. • Remove the multiplier register • Place the multiplier value in the lower half of the product register Multiplication & Division Algorithms

  14. Solution #3: Operations Multiplication & Division Algorithms

  15. Solution #3: Example Iter Step Multiplicand Product 0 Initial Values 1100 0000 1001 1 Product[0]=1  Prod+Mcand 1100 1100 1001 Shift product right 1100 0110 0100 2 Product[0]=0  Do nothing 1100 0110 0100 Shift product right 1100 0011 0010 3 Product[0]=0  Do nothing 1100 0011 0010 Shift product right 1100 0001 1001 4 Product[0]=1  Prod+Mcand 1100 1101 1001 Shift product right 1100 0110 1100 Multiplication & Division Algorithms

  16. Solution #3: Hardware Multiplicand 32 bits Add 32-bit ALU Shift Right Product Control Write 64 bits Upper 32 bits Multiplier LSB Multiplication & Division Algorithms

  17. Signed Multiplication • Previous algorithms work for unsigned. • We could: • convert both multiplier and multiplicand to positive before starting, but remember the signs. • adjust the product to have the right sign (might need to negate the product). • Set the sign bit to make the number negative if the multiplicand and multiplier disagree in sign • Positive × Positive = Positive • Negative × Negative = Positive • Positive × Negative = Negative • Negative × Positive = Negative Multiplication & Division Algorithms

  18. Supporting Signed Integers • We can adjust the previous algorithm to work with signed integers • make sure each shift is an arithmetic shift • right shift – extend the sign bit (keep the MS bit the same instead of shifting in a 0). • Since addition works for signed numbers, the multiply algorithm will now work for signed numbers. Multiplication & Division Algorithms

  19. 1110 x 0011 (-2 x 3) multiplier is rightmost 4 bits 1st partial product in left 4 bits Shift Right Result is 2s complement Multiplication & Division Algorithms

  20. Signed Third Multiplication Algorithm Multiplication & Division Algorithms

  21. Improving the speed with Combinational Array Multiplier Multiplication & Division Algorithms

  22. Combinational Array Multiplier Multiplication & Division Algorithms

  23. Combinational Array Multiplier3 bit Example Multiplication & Division Algorithms

  24. Booth’s Algorithm • Requires that we can do an addition or a subtraction each iteration (not always an addition). • Uses the following property • the value of any consecutive string of 1s in a binary number can be computed with one subtraction. Multiplication & Division Algorithms

  25. A different way to compute integer values 0110 23-21 (8-2=6) 0011111000 28-23 (256-8 = 248) 23 21 28 23 Multiplication & Division Algorithms

  26. A little more complex example 010011010 28-27 + 25-23 + 22-21 256-128 + 32-8 + 4-2 28 27 22 21 25 23 Multiplication & Division Algorithms

  27. An overview of Booth’s Algorithm • When doing multiplication, strings of 0s in the multiplier require only shifting (no addition). • When doing multiplication, strings of 1s in the multiplier require operation and shifting. • We need to add or subtract only at positions in the multiplier where there is a transition from a 0 to a 1, or from a 1 to a 0. Multiplication & Division Algorithms

  28. Booth Explanation • Booth also works for negative numbers • Booth Algorithm • Add additional bit to the right of product • Use right two bits of product to determine action • Use arithmetic right shift ( ) End of string Beginning of string 0 0 1 1 1 1 0 0 Middle of string Multiplication & Division Algorithms

  29. Shifting • The second step of the algorithm is the same as before: shift the product/multiplier right one bit. • Arithmetic shift needed for signed arithmetic. • The bit shifted off the right is saved and used by the next step 1 (which looks at 2 bits). Booth’s Algorithm Multiplication & Division Algorithms

  30. Booth Example • Consider the same example, but think of it as a signed multiplication (-4×-7=28) Iter Step Multiplicand Product 0 Initial Values 1100 0000 1001 0 1 Product=10  Prod-Mcand 1100 0100 1001 0 Shift product right 1100 0010 0100 1 2 Product=01  Prod+Mcand 1100 1110 0100 1 Shift product right 1100 1111 0010 0 3 Product=00  Do nothing 1100 1111 0010 0 Shift product right 1100 1111 1001 0 4 Product=10  Prod-Mcand 1100 0011 1001 0 Shift product right 1100 0001 1100 1 Multiplication & Division Algorithms

  31. Multiply in MIPS • Product stored in two 32 bit registers called Hi and Low mult $s0, $s1 # $s0 * $s1 high/low multu $s0, $s1 # $s0 * $s1 unsigned • Results are moved from Hi/Low mfhi $t0 # $t0 = Hi mflo $t0 # $t0 = Low • Pseudoinstruction mul $t0, $s0, $s1 # $t0 = $s0 * $s1 Multiplication & Division Algorithms

  32. Divide • Long-hand division (108 ÷ 12 = 9) 1 0 0 1 (n bit Quotient) +--------------- +----------------- 1 1 0 0 | 1 1 0 1 1 0 0 (Divisor) | (Dividend) - 1 1 0 0 --------- 0 0 1 1 - 0 0 0 0 --------- 0 1 1 0 - 0 0 0 0 --------- 1 1 0 0 - 1 1 0 0 --------- 0 0 0 0 (Remainder) N + 1 Steps Multiplication & Division Algorithms

  33. Divide Solution #1 rem = rem - div if rem < 0 then // divisor too big rem = rem + div quo <<= 1 LSB(quo) = 0 else // can divide quo <<= 1 LSB(quo) = 1 fi div >>= 1 repeat unless done • Solution #1 • Start with quotient = 0, remainder = dividend, and divisor’s top bits set • On each iteration set remainder to be remainder – divisor • If large enough (remainder  0), then shift quotient left and set rightmost to 1 • If not large enough (remainder < 0), then set remainder to remainder + divisor (restore) • Shift divisor right • Continue for n+1 (33) iterations Multiplication & Division Algorithms

  34. Divide Solution #1 Multiplication & Division Algorithms

  35. Solution #1: Hardware Shift Right Divisor 64 bits Shift Left Quotient 64-bit ALU 32 bits Write Remainder Control 64 bits MSB Multiplication & Division Algorithms

  36. Multiplication & Division Algorithms

  37. 00000111 / 0010 initial values after subtraction after restore shift right final remainder final quotient Multiplication & Division Algorithms

  38. 4 2 1 5 3 Divisor ShRight 64 bit ShLeft Quotient 64-bit 32 bit Remainder Write Control 64 bit Division Example: 1001001/0101 QuotientDivisorRemainder xxxx0101000001001001 Initial Values (Divisor in LHS) • 1a.Rem. <-- Rem-Divisor - • 1b.Rem.<0, Add Div., LSh Q, Q0=0; RSh Div. xxxx0101000011111001 • 2a.Rem. <-- Rem-Divisor xxx00010100001001001 • 2b.Rem>=0, LSh Q, Q0=1; RSh Div. - xxx00010100000100001 • 3a.Rem. <-- Rem-Divisor • 3b.Rem>=0, LSh Q, Q0=1; RSh Div. xx010001010000100001 - • 4a.Rem. <-- Rem-Divisor xx010001010000001101 • 4b.Rem>=0, LSh Q, Q0=1; RSh Div. x0110000101000001101 • 5a.Rem. <-- Rem-Divisor - • 5b.Rem<0, Add Div., LSh Q, Q0=0; RSh Div. x0110000101000000011 01110000010100000011 - 01110000010111111110 11100000001000000011 1001001/0101 = 1110 rem 001173/5 = 14 rem 3 N+1 Steps, but first step cannot produce a 1. Multiplication & Division Algorithms

  39. Issues and Alternative • Just as before • Half of the divisor bits are always 0 • Either high or low bits are 0, even as shifted • Half of the 64 bit adder is therefore wasted • Solution #2 • Instead of shifting divisor right, shift the remainder left • Adder only needs to be 32 bits wide • Can also remove iteration by switching order to shift and then subtract • Remainder is in left half of register Multiplication & Division Algorithms

  40. Solution #2: Hardware Divisor 32 bits Shift Left Quotient 32-bit ALU 32 bits Shift Left Remainder Control Write 64 bits MSB Multiplication & Division Algorithms

  41. 1 2 3 4 Divisor 32 bit ShLeft Quotient 32 bit 32-bit Write Control ShLeft LH Rem. RH Rem. 64 bit Improved Divider: 1001001/0101 Initial Values QuotientDivisorRemainder xxxx010101001001 • 0. LSh Rem • 1a.Rem. <-- Rem-Divisor xxxx01011001001x - • 1b.Rem>=0, LSh Q, Q0=1; LSh Rem. xxxx01010100001x • 2a.Rem. <-- Rem-Divisor xxx10101100001xx • 2b.Rem>=0, LSh Q, Q0=1; LSh Rem. - xxx10101001101xx • 3a.Rem. <-- Rem-Divisor xx11010101101xxx • 3b.Rem>=0, LSh Q, Q0=1; LSh Rem. - • 4a.Rem. <-- Rem-Divisor xx11010100011xxx • 4b.Rem<0, Add Div., LSh Q, Q0=0 x1110101 0011xxxx - x11101011110xxxx 111001010011xxxx 1001001/0101 = 1110 rem 001173/5 = 14 rem 3 Multiplication & Division Algorithms

  42. Issues and Alternative • Just as before, half of the remainder register is useless at the beginning • At the end, the quotient register becomes useless • Solution #3 • Remove the quotient register • Place the quotient in the lower half of the remainder register • Need to unshift in the last step to account for off-by-one Multiplication & Division Algorithms

  43. D i v i s o r quotient 3 2 b i t s 3 2 - b i t A L U S h i f t r i g h t C o n t r o l R e m a i n d e r S h i f t l e f t t e s t W r i t e 6 4 b i t s Further ModificationsSolution#3 • Same space savings as with multiplication: • use right ½ of remainder register to hold the quotient. Multiplication & Division Algorithms

  44. S t a r t 2 . S u b t r a c t t h e D i v i s o r r e g i s t e r f r o m t h e l e f t h a l f o f t h e R e m a i n d e r r e g i s t e r a n d p l a c e t h e r e s u l t i n t h e l e R e m a i n d e r < 0 T e s t R e m a i n d e r 3 a . S h i f t t h e R e m a i n d e r r e g i s t e r t o t h e 3 b . R e s t o r e t h e o r i g i n a l v a l u e b y a d d i n g l e f t , s e t t i n g t h e n e w r i g h t m o s t b i t t o 1 t h e D i v i s o r r e g i s t e r t o t h e l e f t h a l f o f t h e R e m a i n d e r r e g i s t e r a n d p l a c e t h e s u m i n t h e l e f t h a l f o f t h e R e m a i n d e r r e g i s t e r . A l s o s h i f t t h e R e m a i n d e r r e g i s t e r t o t h e l e f t , s e t t i n g t h e n e w r i g h t m o s t b i t t o 0 N o : < 3 2 r e p e t i t i o n s 3 2 n d r e p e t i t i o n ? Y e s : 3 2 r e p e t i t i o n s D o n e . S h i f t l e f t h a l f o f R e m a i n d e r r i g h t 1 b i t Divide Solution #3 1 . S h i f t t h e R e m a i n d e r r e g i s t e r l e f t 1 b i t rem <<= 1 rem -= (div >> 32) if rem < 0 then rem += (div >> 32) rem <<= 1 LSB(rem) = 0 else rem <<= 1 LSB(rem) = 1 fi repeat unless done Correct remainder f t h a l f o f t h e R e m a i n d e r r e g i s t e r > R e m a i n d e r 0 – Multiplication & Division Algorithms

  45. Solution #3: Example Multiplication & Division Algorithms

  46. 1 2 3 4 Divisor 32 bit 32-bit Write Control ShLeft LH Rem. Rem-Quot. 64 bit Improved Improved Divider: 1001001/0101 Initial Values DivisorRemainder-Quotient 010101001001 • 0. LSh Rem-Quo. • 1a.Rem <-- Rem-Divisor 010110010010 - • 1b.Rem>=0, LSh Rem-Quo, Q0=1 010101000010 • 2a.Rem. <-- Rem-Divisor 010110000101 • 2b.Rem>=0, LSh Rem-Quo,Q0=1 - 010100110101 • 3a.Rem. <-- Rem-Divisor 010101101011 • 3b.Rem>=0, LSh Rem-Quo, Q0=1 - • 4a.Rem. <-- Rem-Divisor 010100011011 • 4b.Rem<0, Add Div., LSh Rem-Quo, Q0=0 010100110111 - 010111100111 010101101110 • Final: RSh Rem 1 010100111110 1001001/0101 = 1110 rem 001173/5 = 14 rem 3 Multiplication & Division Algorithms

  47. Signed Division • Same process as naïve integer multiply • Make divisor and dividend positive • Negate quotient if signs of divisor and dividend disagree • Set sign of remainder • Dividend = Quotient × Divisor + Remainder • Sign should match dividend Multiplication & Division Algorithms

  48. Divide in MIPS • Quotient/Remainder stored in two 32 bit registers called Hi and Low div $s0, $s1 # $s0 / $s1 high/low divu $s0, $s1 # $s0 / $s1 unsigned • Results are moved from Hi/Low mfhi $t0 # $t0 = Hi mflo $t0 # $t0 = Low • Pseudoinstructions div $t0, $s0, $s1 # $t0 = $s0 / $s1 rem $t0, $s0, $s1 # $t0 = $s0 % $s1 div $s0,$s1Lo = $s0/$s1 (integer)Hi = $s0 % $s1 Multiplication & Division Algorithms

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