Ch 9. Memory, CPLDs, and FPGAs
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Ch 9. Memory, CPLDs, and FPGAs. 1. Read-Only Memory. Az : output polarity control Az = 0 output active low Az = 1 output active high. 9.1.1 Using ROMs for “Random” Combinational Logic Function. 9.1.1 Using ROMs for “Random” Combinational Logic Function.

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Ch 9. Memory, CPLDs, and FPGAs

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Ch 9 memory cplds and fpgas

Ch 9. Memory, CPLDs, and FPGAs

1. Read-Only Memory


Ch 9 memory cplds and fpgas

Az : output polarity control

Az = 0 output active low

Az = 1 output active high


Ch 9 memory cplds and fpgas

  • 9.1.1 Using ROMs for “Random” Combinational Logic Function


Ch 9 memory cplds and fpgas

  • 9.1.1 Using ROMs for “Random” Combinational Logic Function


Ch 9 memory cplds and fpgas

  • 9.1.1 Using ROMs for “Random” Combinational Logic Function


Ch 9 memory cplds and fpgas

  • 9.1.1 Using ROMs for “Random” Combinational Logic Function


Ch 9 memory cplds and fpgas

  • 9.1.1 Using ROMs for “Random” Combinational Logic Function


Ch 9 memory cplds and fpgas

  • 9.1.1 Using ROMs for “Random” Combinational Logic Function


Ch 9 memory cplds and fpgas

  • 9.1.2 Internal ROM Structure

If diode present, 1

Otherwise, Ø


Ch 9 memory cplds and fpgas

  • 9.1.2 Internal ROM Structure

Diodes are missing, then

D3 – D0 = 0111 instead of

0010


Ch 9 memory cplds and fpgas

  • 9.1.3 Two-Dimensional Decoding

To reduce decoding complexity -> 7 to 128 decoder is huge

-> instead, 3 – to 8 decoder + 16 – to – 1 MUX


Ch 9 memory cplds and fpgas

  • 9.1.3 Two-Dimensional Decoding

If tr exist, 1

Otherwise, Ø


Ch 9 memory cplds and fpgas

  • 9.1.3 Two-Dimensional Decoding


Ch 9 memory cplds and fpgas

  • 9.1.4 Commercial ROM Types


Ch 9 memory cplds and fpgas

  • 9.1.4 Commercial ROM Types


Ch 9 memory cplds and fpgas

  • 9.1.4 Commercial ROM Types


Ch 9 memory cplds and fpgas

  • 9.1.5 ROM Control Inputs and Timing

Three state bus

OE : output enable

CS : chip select

OE & CS

must be assecped

32k x 8bit ROM x 4 = 128kbytes

(= 215 x 4 = 217) 17address bits


Ch 9 memory cplds and fpgas

  • 9.1.5 ROM Control Inputs and Timing


Ch 9 memory cplds and fpgas

  • 9.1.5 ROM Control Inputs and Timing


Ch 9 memory cplds and fpgas

  • 9.1.6 ROM Applications


Ch 9 memory cplds and fpgas

  • 9.1.6 ROM Applications

In many phone connections, your voice is purposely attennated by

a few decibels to make things work better (page. 729)


Ch 9 memory cplds and fpgas

  • 9.1.6 ROM Applications


Ch 9 memory cplds and fpgas

  • 9.1.6 ROM Applications


Ch 9 memory cplds and fpgas

  • 9.1.6 ROM Applications


Ch 9 memory cplds and fpgas

  • 9.1.6 ROM Applications


Ch 9 memory cplds and fpgas

3. Static RAM

  • 9.3.1 Static-RAM Inputs and Outputs


Ch 9 memory cplds and fpgas

  • 9.3.1 Static-RAM Inputs and Outputs

D-latch when SEL = Ø OUT <- Q

when SEL = WR = Ø D <- IN


Ch 9 memory cplds and fpgas

  • 9.3.2 Static-RAM Internal Structure


Ch 9 memory cplds and fpgas

  • 9.3.3 Static-RAM Timing


Ch 9 memory cplds and fpgas

  • 9.3.3 Static-RAM Timing


Ch 9 memory cplds and fpgas

  • 9.3.4 Standard Static-RAMs


Ch 9 memory cplds and fpgas

  • 9.3.4 Standard Static-RAMs


Ch 9 memory cplds and fpgas

  • 9.3.5 Synchronous SRAM


Ch 9 memory cplds and fpgas

  • 9.3.5 Synchronous SRAM


Ch 9 memory cplds and fpgas

  • 9.3.5 Synchronous SRAM


Ch 9 memory cplds and fpgas

  • 9.3.5 Synchronous SRAM


Ch 9 memory cplds and fpgas

  • 9.3.5 Synchronous SRAM


Ch 9 memory cplds and fpgas

4. Dynamic RAM

  • 9.4.1 Dynamic-RAM Structure

To store 1, word = bit = 1

To store Ø, word 1, bit = Ø

Bit line prechanged between H&1

To read, word = H If cell = 1

Bit line = 1

If cell = Ø, bit line = Ø


Ch 9 memory cplds and fpgas

  • 9.4.1 Dynamic-RAM Structure


Ch 9 memory cplds and fpgas

  • 9.4.1 Dynamic-RAM Structure


Ch 9 memory cplds and fpgas

  • 9.4.1 Dynamic-RAM Structure


Ch 9 memory cplds and fpgas

  • 9.4.2 SDRAM Timing


Ch 9 memory cplds and fpgas

  • 9.4.2 SDRAM Timing


Ch 9 memory cplds and fpgas

  • 9.4.2 SDRAM Timing


Ch 9 memory cplds and fpgas

  • 9.4.2 SDRAM Timing


Ch 9 memory cplds and fpgas

5. Complex Programmable Logic Devices


Ch 9 memory cplds and fpgas

  • 9.5.1 Xilinx XC9500 CPLD Family


Ch 9 memory cplds and fpgas

  • 9.5.1 Xilinx XC9500 CPLD Family


Ch 9 memory cplds and fpgas

  • 9.5.2 Function-Block Architecture


Ch 9 memory cplds and fpgas

  • 9.5.2 Function-Block Architecture


Ch 9 memory cplds and fpgas

  • 9.5.3 Input/Output-Block Architecture


Ch 9 memory cplds and fpgas

  • 9.5.4 Switch Matrix


Ch 9 memory cplds and fpgas

6. Field-Programmable Gate Arrays

  • 9.6.1 Xilinx XC4000 FPGA Family


Ch 9 memory cplds and fpgas

  • 9.6.1 Xilinx XC4000 FPGA Family


Ch 9 memory cplds and fpgas

  • 9.6.1 Xilinx XC4000 FPGA Family

F&G perform any combination

Logic function of 4 inputs H for three inputs


Ch 9 memory cplds and fpgas

  • 9.6.3 Input/Output Block


Ch 9 memory cplds and fpgas

  • 9.6.3 Input/Output Block


Ch 9 memory cplds and fpgas

  • 9.6.4 Programmable Interconnect


Ch 9 memory cplds and fpgas

  • 9.6.4 Programmable Interconnect


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