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Electrical Data Transmission on Flex Cables at 320 Mbps

Electrical Data Transmission on Flex Cables at 320 Mbps. Vitaliy Fadeyev, Peter Manning, Jason Nielsen Santa Cruz Institute for Particle Physics University of California, Santa Cruz. LBL-SLAC-UCSC meeting 20 June 2008. Outline. Have shown some results during meetings in last several months.

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Electrical Data Transmission on Flex Cables at 320 Mbps

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  1. Electrical Data Transmissionon Flex Cables at 320 Mbps Vitaliy Fadeyev, Peter Manning, Jason Nielsen Santa Cruz Institute for Particle Physics University of California, Santa Cruz LBL-SLAC-UCSC meeting 20 June 2008

  2. Outline • Have shown some results during meetings in last several months. • This is an update/summary. • Investigating LVDS transmission on flex cable stripline at speeds up to 320 Mbps over 60-70 cm • Results at waveform (eye diagram) level currently. • Investigation of different loads and trace geometry. V. Fadeyev (Santa Cruz)

  3. Testing Hardware Setup Xilinx ML-310 (Virtex 2 Pro) National DS25BR100EVK V. Fadeyev (Santa Cruz)

  4. Prototype Stave Cable • Thanks to Carl, an early version of SCT stave. • 50 cm long stripline • Taps every 10 cm Shields top and bottom bonded together Bond to straight traces on cable edge V. Fadeyev (Santa Cruz)

  5. Assumptions • Recall from architecture: we are planning for point-to-point transmission for data, and multiple “tap points” for the clock distribution. • Except… 4 FE ASICs sharing the dataout bus is a possible choice for the upgrade ( without a dedicated module controller.) V. Fadeyev (Santa Cruz)

  6. Investigated Trace geometry effects The available cable has a several types of striplines. V. Fadeyev (Santa Cruz)

  7. Effect of the Tap Put 10 pF load at the source in two ways: 1) serially 2) via 2 cm long tap. Serial insertion With 2 cm long tap V. Fadeyev (Santa Cruz)

  8. Cross-Talk Drive differential pair with 100 MHz clock (blue) Measure cross-talk signal on adjacent terminated trace (orange) separated by 100 microns (same as stripline width) At source end At termination end Note different scales: cross-talk amplitude is less than 5% . V. Fadeyev (Santa Cruz)

  9. Conclusions • Indications for satisfactory performance for several variations of stripline geometry. • For multi-tap scenario, the performance depends on “tap” loads. • “Clumped capacitance” scenario (for module-control-less architecture) is ok. • There is some effect of tap length, likely to be small for realistic loads and non-complicated trace layouts. • Cross-talk between nearby traces is small. V. Fadeyev (Santa Cruz)

  10. Next Steps • Bringing more reality – latches and “real” HEP ASICs with LVDS drivers. • Transitioning to more quantitative measurements -- commissioning our home-made Bit Error Rate Test system based on FPGA board • Follow up with software modeling • System-level tests with full stave readout • Custom-made cables with proper routing • Serial powering and effect of balancing the protocols? V. Fadeyev (Santa Cruz)

  11. Backup Slides V. Fadeyev (Santa Cruz)

  12. Eye Diagrams with 4 x 2 pF loads Worst cases are near the source (tap 1). Straight trace Zigzag trace V. Fadeyev (Santa Cruz)

  13. Amplitude with Capacitive Load Put LVDS repeaters at each tap: input capacitance 0.6 pF each Waveforms shown of 320 MHz clock from a repeater along cable Maurice has pointed out that a regular clock is the easiest signal to transmit. This is convenient because the clock sees multiple taps. A typical LVDS output amplitude for most signals is 650 mV V. Fadeyev (Santa Cruz)

  14. Loaded Prototype Cable We expect approx 2 pF input capacitance from LVDS receivers (Chip on our piggy-back board has 0.6 pF stray capacitance) Add 2 pF across each tap to simulate this load Confirm with TDR that Vp is 0.60 ± 0.05 without loading End termination studies with potentiometer only confirm that the impedance is between 50 and 100. V. Fadeyev (Santa Cruz)

  15. Higher Input Capacitances Increase capacitive loads on prototype from 2 to 10 pF This may be too much for the receivers to distinguish proper levels Aside: we were able to “break” LVDS receiver output only with very low cable termination values V. Fadeyev (Santa Cruz)

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