Chapter 3 digital logic structures
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Chapter 3 Digital Logic Structures. Transistor: Building Block of Computers. Microprocessors contain millions of transistors Intel Pentium II: 7 million Compaq Alpha 21264: 15 million Intel Pentium III: 28 million Logically, each transistor acts as a switch

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Chapter 3 Digital Logic Structures

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Chapter 3 digital logic structures

Chapter 3Digital LogicStructures


Transistor building block of computers

Transistor: Building Block of Computers

  • Microprocessors contain millions of transistors

    • Intel Pentium II: 7 million

    • Compaq Alpha 21264: 15 million

    • Intel Pentium III: 28 million

  • Logically, each transistor acts as a switch

  • Combined to implement logic functions

    • AND, OR, NOT

  • Combined to build higher-level structures

    • Adder, multiplexor, decoder, register, …

  • Combined to build processor

    • LC-2


Simple switch circuit

Simple Switch Circuit

  • Switch open:

    • No current through circuit

    • Light is off

    • Vout is + 5V

  • Switch closed:

    • Short circuit across switch

    • Current flows

    • Light is on

    • Vout is 0V

Switch-based circuitscan easily represent two states:

on/off, open/closed, voltage/no voltage.


Logical and

LOGICAL AND:


N type mos transistor

N-type MOS Transistor

  • MOS = Metal Oxide Semiconductor

    • two types: N-type and P-type

  • N-type

    • when Gate has positive voltage,short circuit between #1 and #2(switch closed)

    • when Gate has zero voltage,open circuit between #1 and #2(switch open)

Gate = 1

Gate = 0

Terminal #2 must be

connected to GND (0V).


P type mos transistor

P-type MOS Transistor

  • P-type is complementary to N-type

    • when Gate has positive voltage,open circuit between #1 and #2(switch open)

    • when Gate has zero voltage,short circuit between #1 and #2(switch closed)

Gate = 1

Gate = 0

Terminal #1 must be

connected to +2.9V.


Logic gates

Logic Gates

  • Use switch behavior of MOS transistorsto implement logical functions: AND, OR, NOT.

  • Digital symbols:

    • recall that we assign a range of analog voltages to eachdigital (logic) symbol

    • assignment of voltage ranges depends on electrical properties of transistors being used

      • typical values for "1": +5V, +3.3V, +2.9V

      • from now on we'll use +5V


Cmos circuit

CMOS Circuit

  • Complementary MOS

  • Uses both N-type and P-type MOS transistors

    • P-type

      • Attached to + voltage

      • Pulls output voltage UP when input is zero

    • N-type

      • Attached to GND

      • Pulls output voltage DOWN when input is one

  • For all inputs, make sure that output is either connected to GND or to +,but not both!


Inverter not gate

Inverter (NOT Gate)

Truth table


Nor gate

NOR Gate

Note: Serial structure on top, parallel on bottom.


Or gate

OR Gate

Add inverter to NOR.


Nand gate and not

NAND Gate (AND-NOT)

Note: Parallel structure on top, serial on bottom.


And gate

AND Gate

Add inverter to NAND.


Basic logic gates

Basic Logic Gates


Fundamental properties of boolean algebra

Fundamental Properties of boolean algebra:

Commutative:

  • X + Y = Y + X

  • X . Y = Y . X

    Associative:

  • ( X + Y) + Z = X + (Y + Z)

  • ( X . Y) . Z = X . (Y . Z)

    Distributive:

  • X . (Y + Z) = (X . Y) + (X . Z)

  • X + (Y . Z) = (X + Y) . (X + Z)

    Identity:

  • X + 0 = X

  • X . 1 = X

    Complement:

  • X +X’ = 1

  • X . X’ = 0


Chapter 3 digital logic structures

  • X+1

  • X+0

  • X.X

  • X.1

  • X.0

  • X+XY


More than 2 inputs

More than 2 Inputs?

  • AND/OR can take any number of inputs.

    • AND = 1 if all inputs are 1.

    • OR = 1 if any input is 1.

    • Similar for NAND/NOR.

  • Can implement with multiple two-input gates,or with single CMOS circuit.


Practice

Practice

  • Implement a 3-input NOR gate with CMOS.


Logical completeness

Logical Completeness

  • Can implement ANY truth table with AND, OR, NOT.

1. AND combinations that yield a "1" in the truth table.

2. OR the resultsof the AND gates.


Practice1

A

B

C

Practice

  • Implement the following truth table.


Another example

X

Y

Z

Output

Another example:

We want to build a circuit that has 3 binary inputs.

This CKT is On if the inputs are X’Y’Z or X’YZ’ .


Xor gate

A + B

A + B

XOR gate:

  • A XOR B= A.B’+A’.B

  • A + B

A

B

A

B

A.B’+A’.B


Demorgan s law

DeMorgan's Law

  • Converting AND to OR (with some help from NOT)

  • Consider the following gate:

To convert AND to OR

(or vice versa),

invert inputs and output.

Same as A+B


Chapter 3 digital logic structures

OR Truth

table

  • DeMorgan Law:

  • A+B= (A’ . B’)’

  • A.B=(A’+B’)’

AND Truth

table


Chapter 3 digital logic structures

  • A’.B = (A+B’)’


Chapter 3 digital logic structures

  • Build the following logical expression using AND, Not Gates only:

  • F=X.Y+Z’

    =((X.Y)’.Z’’)’

    =((X.Y)’.Z)’

    Another example:

  • F= XYZ+Y’Z+XZ’

    = ( (XYZ)’.(Y’Z)’.(XZ’)’ )’


From demorgans law

From Demorgans law

  • A+B= (A’.B’)’

  • (A+B)’= (A’.B’)’’=A’.B’

  • A.B= (A’+B’)’

  • (A.B)’= (A’+B’)’’=A’+B’


Chapter 3 digital logic structures

  • Simplify the following boolean expression

  • F= (A’BC + C + A + D )’

  • = ( A’BCC’ + (A’BC)’C +A+D)’

  • = ( A’B. 0 + (A’BC)’C +A+D)’

  • = ( 0 + (A’BC)’C +A+D)’

  • = ( (A+B’+C’)C+A+D)’

  • = ( AC+B’C+C’C+A+D)’

  • = ( AC+B’C+ 0 + A +D)’

  • = (AC+A + B’C + D)’

  • = ( A + B’C + D)’

  • = A’ (B’C)’ D’

  • = A’ D’( B+C’)

  • = A’BD’+A’C’D’


Simplification using boolean algebra

Simplification using boolean algebra:

  • We have the following truth table for logical circuit and we want to implement this in the minimum number of gates:

F=A’B’C+A’BC+AB’C’+AB’C+ABC’

= A’B’C+A’BC+AB’(C+C’)+ABC’

= A’C(B+B’) +AB’ +ABC’

= A’C+AB’+AC’(B+B’) ;we can reuse AB’C’

=A’C+AB’+AC’


Another example1

Another example:

F=A’B’C+A’BC+AB’C+ABC’+ABC

= A’C(B+B’)+AB’C+ABC’+ABC

= A’C + AC(B’+B) +ABC’

= A’C+AC+ AB(C+C’)

=A’C+AC+AB

= C(A+A’)+AB

= C+AB


Karnaugh maps

Karnaugh Maps

  • Karnaugh map : is a representation for the truth table in a graphical way, which makes the simplification of any boolean function easier.

  • For 3 input boolean function the Karnaugh map will be as follows :

BC

A

As we can see, each cell represent one raw of the truth table

Next step is to fill the map using the truth table output.


Simplification using karnaugh

Simplification using Karnaugh:

  • Let us resolve the previous examples using karnaugh map:

BC

A

F=A’C+B’C+AC’


Chapter 3 digital logic structures

  • Resolve the same example in another way:

BC

F=A’C+AB’+AC’


Karnaugh map for 4 input boolean function

Karnaugh map for 4 input boolean function

CD

AB


Chapter 3 digital logic structures

  • Assume we have the boolean function F with 4 inputs:

  • F(A,B,C,D)= ∑ (0,1 ,4, 6, 8,11,13, 15)

  • Make the truth table for this function

  • Write the boolean equation for this function (Before simplification)

  • Simplify this function using karnaugh map technique

  • Draw the simplified equation.


Summary

Summary

  • MOS transistors are used as switches to implementlogic functions.

    • N-type: connect to GND, turn on (with 1) to pull down to 0

    • P-type: connect to +2.9V, turn on (with 0) to pull up to 1

  • Basic gates: NOT, NOR, NAND

    • Logic functions are usually expressed with AND, OR, and NOT

  • Properties of logic gates

    • Completeness

      • can implement any truth table with AND, OR, NOT

    • DeMorgan's Law

      • convert AND to OR by inverting inputs and output


Building functions from logic gates

Building Functions from Logic Gates

  • We've already seen how to implement truth tablesusing AND, OR, and NOT -- an example of combinational logic.

  • Combinational Logic Circuit

    • output depends only on the current inputs

    • stateless

  • Sequential Logic Circuit

    • output depends on the sequence of inputs (past and present)

    • stores information (state) from past inputs

  • We'll first look at some useful combinational circuits,then show how to use sequential circuits to store information.


Decoder

Decoder

  • n inputs, 2n outputs

1

Y0

A

0

1

1

0

0

0

1

1

1

Y1

1

Y2

B

1

Y3


Decoder1

Decoder

  • n inputs, 2n outputs

    • exactly one output is 1 for each possible input pattern

2-bit

decoder


Chapter 3 digital logic structures

3x8 decoder

0

1

2

3

4

5

6

7


Build the following truth table using decoder and or gate

Build the following truth table using Decoder and OR gate

3x8 decoder

0

1

2

3

4

5

6

7


Multiplexer mux

Multiplexer (MUX)

  • n-bit selector and 2n inputs, one output

0

1

I0

I1

I2

I3

1

1

0

S1 S0

0 0

0 1


Multiplexer mux1

Multiplexer (MUX)

  • n-bit selector and 2n inputs, one output

    • output equals one of the inputs, depending on selector

4-to-1 MUX


Full adder

Full Adder

  • Add two bits and carry-in,produce one-bit sum and carry-out.

  • S = A + B + Cin

  • Cout = A.B+A.C+B.C


Full adder1

Full Adder

  • Add two bits and carry-in,produce one-bit sum and carry-out.

3x8 decoder

0

1

A

B

Cin

S

2

3

4

5

C

6

7


Four bit adder

Four-bit Adder


Combinational vs sequential

Combinational vs. Sequential

  • Combinational Circuit

    • always gives the same output for a given set of inputs

      • ex: adder always generates sum and carry,regardless of previous inputs

  • Sequential Circuit

    • stores information

    • output depends on stored information (state) plus input

      • so a given input might produce different outputs,depending on the stored information

    • example: ticket counter

      • advances when you push the button

      • output depends on previous state

    • useful for building “memory” elements and “state machines”


R s latch simple storage element

R-S Latch: Simple Storage Element

  • R is used to “reset” or “clear” the element – set it to zero.

  • S is used to “set” the element – set it to one.

  • If both R and S are one, out could be either zero or one.

    • “quiescent” state -- holds its previous value

    • note: if a is 1, b is 0, and vice versa

1

1

0

1

1

0

1

0

1

1

0

0

1

1


Clearing the r s latch

Clearing the R-S latch

  • Suppose we start with output = 1, then change R to zero.

1

0

1

1

0

1

0

Output changes to zero.

1

1

1

0

1

1

0

0

0

Then set R=1 to “store” value in quiescent state.


Setting the r s latch

Setting the R-S Latch

  • Suppose we start with output = 0, then change S to zero.

1

1

0

1

0

Output changes to one.

1

0

0

1

0

1

1

Then set S=1 to “store” value in quiescent state.


R s latch summary

R-S Latch Summary

  • R = S = 1

    • hold current value in latch

  • S = 0, R=1

    • set value to 1

  • R = 0, S = 1

    • set value to 0

  • R = S = 0

    • both outputs equal one

    • final state determined by electrical properties of gates

    • Don’t do it!


Gated d latch

Gated D-Latch

  • Two inputs: D (data) and WE (write enable)

    • when WE = 1, latch is set to value of D

      • S = NOT(D), R = D

    • when WE = 0, latch holds previous value

      • S = R = 1


Register

Register

  • A register stores a multi-bit value.

    • We use a collection of D-latches, all controlled by a common WE.

    • When WE=1, n-bit value D is written to register.


Representing multi bit values

Representing Multi-bit Values

  • Number bits from right (0) least significant bit LSb to left (n-1) most significant bit MSb

    • just a convention -- could be left to right, but must be consistent

  • Use brackets to denote range:D[l:r] denotes bit l to bit r, from left to right

  • May also see A<14:9>, A14:9especially in hardware block diagrams.

0

15

A = 0101001101010101

A[2:0] = 101

A[14:9] = 101001


Memory

Memory

  • Now that we know how to store bits,we can build a memory – a logical k × m array of stored bits.

Address Space:

number of locations(usually a power of 2)

k = 2n

locations

Addressability:

number of bits per location(e.g., byte-addressable)

m bits


2 2 x 3 memory

00

1

22 x 3 Memory

1 0 1

word WE

word select

input bits

address

write

enable

address

decoder

output bits


2 2 x 3 memory1

00

22 x 3 Memory

1 0 0

word WE

word select

input bits

address

0

write

enable

1 0 1

1 0 1

address

decoder

output bits


Chapter 3 digital logic structures

  • IF we want to build a memory of size 1024 word each word 8 bit

  • What is the size of the decoder needed

  • How many d- flip flops do we need

  • How many And Gates do we need

  • How many OR gates do we need

  • How many inputs for the OR gates needed


More memory details

More Memory Details

  • This is not the way actual memory is implemented.

    • fewer transistors, much more dense, relies on electrical properties

  • But the logical structure is very similar.

    • address decoder

    • word select line

    • word write enable

  • Two basic kinds of RAM (Random Access Memory)

  • Static RAM (SRAM)

    • fast, maintains data without power

  • Dynamic RAM (DRAM)

    • slower but denser, bit storage must be periodically refreshed

Also, non-volatile memories: ROM, PROM, flash, …


State machine

State Machine

  • Another type of sequential circuit

    • Combines combinational logic with storage

    • “Remembers” state, and changes output (and state) based on inputs and current state

State Machine

Inputs

Outputs

Combinational

Logic Circuit

Storage

Elements


Combinational vs sequential1

4

1

8

4

30

25

5

20

10

15

Combinational vs. Sequential

  • Two types of “combination” locks

Combinational

Success depends only onthe values, not the order in which they are set.

Sequential

Success depends onthe sequence of values

(e.g, R-13, L-22, R-3).


State

State

  • The state of a system is a snapshot ofall the relevant elements of the systemat the moment the snapshot is taken.

  • Examples:

    • The state of a basketball game can be represented bythe scoreboard.

      • Number of points, time remaining, possession, etc.

    • The state of a tic-tac-toe game can be represented bythe placement of X’s and O’s on the board.


State of sequential lock

State of Sequential Lock

  • Our lock example has four different states,labelled A-D:A: The lock is not open,and no relevant operations have been performed.

  • B:The lock is not open,and the user has completed the R-13 operation.

  • C:The lock is not open,and the user has completed R-13, followed by L-22.

  • D:The lock is open.


State diagram

State Diagram

  • Shows states and actions that cause a transition between states.


Finite state machine

Finite State Machine

  • A description of a system with the following components:

  • A finite number of states

  • A finite number of external inputs

  • A finite number of external outputs

  • An explicit specification of all state transitions

  • An explicit specification of what causes eachexternal output value.

  • Often described by a state diagram.

    • Inputs may cause state transitions.

    • Outputs are associated with each state (or with each transition).


The clock

The Clock

  • Frequently, a clock circuit triggers transition fromone state to the next.

  • At the beginning of each clock cycle,state machine makes a transition,based on the current state and the external inputs.

    • Not always required. In lock example, the input itself triggers a transition.

“1”

“0”

One

Cycle

time


Implementing a finite state machine

Implementing a Finite State Machine

  • Combinational logic

    • Determine outputs and next state.

  • Storage elements

    • Maintain state representation.

State Machine

Inputs

Outputs

Combinational

Logic Circuit

Storage

Elements

Clock


Storage master slave flipflop

Storage: Master-Slave Flipflop

  • A pair of gated D-latches, to isolate next state from current state.

During 1st phase (clock=1),previously-computed statebecomes current state and issent to the logic circuit.

During 2nd phase (clock=0),next state, computed bylogic circuit, is stored inLatch A.


Storage

Storage

  • Each master-slave flipflop stores one state bit.

  • The number of storage elements (flipflops) neededis determined by the number of states(and the representation of each state).

  • Examples:

    • Sequential lock

      • Four states – two bits

    • Basketball scoreboard

      • 7 bits for each score, 5 bits for minutes, 6 bits for seconds,1 bit for possession arrow, 1 bit for half, …


Complete example

Complete Example

  • A blinking traffic sign

    • No lights on

    • 1 & 2 on

    • 1, 2, 3, & 4 on

    • 1, 2, 3, 4, & 5 on

    • (repeat as long as switchis turned on)

3

4

1

5

2

DANGERMOVERIGHT


Traffic sign state diagram

Traffic Sign State Diagram

Switch on

Switch off

State bit S1

State bit S0

Outputs

Transition on each clock cycle.


Traffic sign truth tables

Traffic Sign Truth Tables

Outputs

(depend only on state: S1S0)

Next State: S1’S0’(depend on state and input)

Switch

Lights 1 and 2

Lights 3 and 4

Light 5

Whenever In=0, next state is 00.


Traffic sign logic

Traffic Sign Logic

Master-slaveflipflop


From logic to data path

From Logic to Data Path

  • The data path of a computer is all the logic used toprocess information.

    • See the data path of the LC-2 on next slide.

  • Combinational Logic

    • Decoders -- convert instructions into control signals

    • Multiplexers -- select inputs and outputs

    • ALU (Arithmetic and Logic Unit) -- operations on data

  • Sequential Logic

    • State machine -- coordinate control signals and data movement

    • Registers and latches -- storage elements


Lc 2 data path

LC-2 Data Path


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